Pub Date : 2016-06-13DOI: 10.1109/iccsp.2015.7322614
M. P. Vaiyshnavi, R. Rathna
The Sleep/Wake up scheduling for Wireless Sensor Networks has become an essential part of its working. The LECSA (Load and Energy Consumption based Scheduling Algorithm) which gives a simplified method for scheduling using a node weighting parameter has been previously introduced and it performs scheduling and data transmission in an efficient manner. Every cluster head has to send the data collected from all its child nodes to the sink following a tree structure. The cluster head should have a radio with a high transmission range. In this work the cluster head finds the nearest active node in the neighbour cluster and then it forwards its data to it by using an energy balanced tree construction which dynamically changes every time and follows a schedule which is created based on the load and residual energy.
无线传感器网络的睡眠/唤醒调度已成为其工作的重要组成部分。LECSA (Load and Energy Consumption based Scheduling Algorithm)给出了一种使用节点权重参数的简化调度方法，并以高效的方式执行调度和数据传输。每个簇头都必须按照树结构将从其所有子节点收集的数据发送到接收器。集群头应该有一个高传输范围的无线电。在这项工作中，簇头在邻近簇中找到最近的活动节点，然后使用能量平衡树结构将其数据转发给它，该结构每次动态变化，并遵循基于负载和剩余能量创建的时间表。
{"title":"Improved scheduling algorithm using dynamic tree construction for wireless sensor networks","authors":"M. P. Vaiyshnavi, R. Rathna","doi":"10.1109/iccsp.2015.7322614","DOIUrl":"https://doi.org/10.1109/iccsp.2015.7322614","url":null,"abstract":"The Sleep/Wake up scheduling for Wireless Sensor Networks has become an essential part of its working. The LECSA (Load and Energy Consumption based Scheduling Algorithm) which gives a simplified method for scheduling using a node weighting parameter has been previously introduced and it performs scheduling and data transmission in an efficient manner. Every cluster head has to send the data collected from all its child nodes to the sink following a tree structure. The cluster head should have a radio with a high transmission range. In this work the cluster head finds the nearest active node in the neighbour cluster and then it forwards its data to it by using an energy balanced tree construction which dynamically changes every time and follows a schedule which is created based on the load and residual energy.","PeriodicalId":174192,"journal":{"name":"2015 International Conference on Communications and Signal Processing (ICCSP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124340142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-12DOI: 10.1109/ICCSP.2015.7322915
K. Keerthana, M. Shanmugaraja, P. MaheshKannan
The objective is to design and simulate the high speed low power pulse triggered flip-flop and to reduce the dynamic power consumption of the flip flop by applying pulse triggering method used for the clocks. Since the on time of the clock pulses are narrowed down, the dynamic power dissipation of the flip flop is greatly reduced. Here, a dedicated pulse generation circuit is used to provide clock pulse with very short on time so that the flip flop switching time is reduced to achieve reduction in the dynamic power dissipation. The design is implemented in GPDK 90nm technology using Cadence Virtuoso Schematic Composer and the Spectre as the simulator.
{"title":"Comparison of conventional flip flops with pulse triggered generation using signal feed through technique","authors":"K. Keerthana, M. Shanmugaraja, P. MaheshKannan","doi":"10.1109/ICCSP.2015.7322915","DOIUrl":"https://doi.org/10.1109/ICCSP.2015.7322915","url":null,"abstract":"The objective is to design and simulate the high speed low power pulse triggered flip-flop and to reduce the dynamic power consumption of the flip flop by applying pulse triggering method used for the clocks. Since the on time of the clock pulses are narrowed down, the dynamic power dissipation of the flip flop is greatly reduced. Here, a dedicated pulse generation circuit is used to provide clock pulse with very short on time so that the flip flop switching time is reduced to achieve reduction in the dynamic power dissipation. The design is implemented in GPDK 90nm technology using Cadence Virtuoso Schematic Composer and the Spectre as the simulator.","PeriodicalId":174192,"journal":{"name":"2015 International Conference on Communications and Signal Processing (ICCSP)","volume":"47 5-6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121003498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-12DOI: 10.1109/ICCSP.2015.7322647
Ishan A. Patil, Vishwas V. Balpande, V. P. Meshram, Ishan S. Chintwar
This paper describes basic arithmetic module using Verilog operations and applies them to the implementation of fast Fourier transform (FFT) processors. The fused operations of like addition subtraction unit. Which can be used for DSP are implementation efficiently with the two fused floating-point operations. When placed and routed using a high performance standard cell technology like vertex -5, the fused arithmetic modules are efficiently works fast and gives user defined facility to modify the butterfly's structure. Also the numerical results of the fused implementations are more accurate, as they use rounding modes is defined as per user requirement. All modules are implemented by using Verilog HDL.
{"title":"Implementation of floating point fused basic arithmetic module using Verilog","authors":"Ishan A. Patil, Vishwas V. Balpande, V. P. Meshram, Ishan S. Chintwar","doi":"10.1109/ICCSP.2015.7322647","DOIUrl":"https://doi.org/10.1109/ICCSP.2015.7322647","url":null,"abstract":"This paper describes basic arithmetic module using Verilog operations and applies them to the implementation of fast Fourier transform (FFT) processors. The fused operations of like addition subtraction unit. Which can be used for DSP are implementation efficiently with the two fused floating-point operations. When placed and routed using a high performance standard cell technology like vertex -5, the fused arithmetic modules are efficiently works fast and gives user defined facility to modify the butterfly's structure. Also the numerical results of the fused implementations are more accurate, as they use rounding modes is defined as per user requirement. All modules are implemented by using Verilog HDL.","PeriodicalId":174192,"journal":{"name":"2015 International Conference on Communications and Signal Processing (ICCSP)","volume":"58 34","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120968077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-12DOI: 10.1109/ICCSP.2015.7322831
A. Halder, Pritam Bhattacharya
Extraction of blood vessels in retinal images provides early diagnosis of different retinopathy diseases (diabetic retinopathy, injury detection, abnormality detection, hemorrhage detection and macular degeneration). This paper presents about the problem of noises and also the blood vessels appearing darker and tiny in the retinal images. This paper introduces a new method for the extraction of retinal blood vessels in retinal fundus images which will be useful to eye specialists in their visual examination of retina and will definitely improve automatic retinal images analysis. In this paper, at first, light reflectance removal technique is used to remove the brighter strips of the images by using green plane of the image. Then, salt and pepper noise and Gaussian noise of the image is removed using median filter and Gaussian filter respectively. After that morphological Bottom Hat Transform is applied to extract the blood vessels. Finally, blood vessels are enhanced using sharpening technique with an unsharp masking. Results are compared with different blood vessel detection algorithms and are found to be encouraging.
{"title":"An application of Bottom Hat transformation to extract blood vessel from retinal images","authors":"A. Halder, Pritam Bhattacharya","doi":"10.1109/ICCSP.2015.7322831","DOIUrl":"https://doi.org/10.1109/ICCSP.2015.7322831","url":null,"abstract":"Extraction of blood vessels in retinal images provides early diagnosis of different retinopathy diseases (diabetic retinopathy, injury detection, abnormality detection, hemorrhage detection and macular degeneration). This paper presents about the problem of noises and also the blood vessels appearing darker and tiny in the retinal images. This paper introduces a new method for the extraction of retinal blood vessels in retinal fundus images which will be useful to eye specialists in their visual examination of retina and will definitely improve automatic retinal images analysis. In this paper, at first, light reflectance removal technique is used to remove the brighter strips of the images by using green plane of the image. Then, salt and pepper noise and Gaussian noise of the image is removed using median filter and Gaussian filter respectively. After that morphological Bottom Hat Transform is applied to extract the blood vessels. Finally, blood vessels are enhanced using sharpening technique with an unsharp masking. Results are compared with different blood vessel detection algorithms and are found to be encouraging.","PeriodicalId":174192,"journal":{"name":"2015 International Conference on Communications and Signal Processing (ICCSP)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133532592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-12DOI: 10.1109/ICCSP.2015.7322706
Sanjay Kumar, B. Ramachandran, S. Bashyam
A dual band circularly polarized (CP) rectangular loop antenna is presented. The antenna comprises two rectangular loops with parasitic rectangular elements inside the driven elements. The bandwidth is enhanced by adding parasitic elements. Antenna structure is situated above a finite ground plane. Two parasitic rectangular loops are connected by a short dipole. To get circular polarization, one gap on the longer side of each rectangular loop is introduced symmetrically with respect to the center of the structure. Each driven loop is fed through short dipole connecting two parasitic rectangular loops. One more feeding is introduced for each driven loop through finite ground plane. Antenna resonance frequency is mainly depends on the circumference of the rectangular loop. The operating bandwidth and symmetry of the pattern is mainly depends on the aspect ratio of the rectangular loop. To get good axial ratio (AR) and return loss, the position of gap and the height of the rectangular loop from the ground plane are very important. The proposed loop antenna has a impedance bandwidth at the frequency of 1.575 GHz and 2.45 GHz are 296 MHz and 600 MHz respectively. Maximum gain of around 8.9 dBi and 7.86 dBi has been achieved at the frequency of 1.575 GHz and 2.45 GHz respectively. The acceptable axial ratio value has been achieved. The proposed antenna can be used for Global Positioning System (GPS) and ISM band applications.
{"title":"Design and implementation of dual-band circularly polarized antenna","authors":"Sanjay Kumar, B. Ramachandran, S. Bashyam","doi":"10.1109/ICCSP.2015.7322706","DOIUrl":"https://doi.org/10.1109/ICCSP.2015.7322706","url":null,"abstract":"A dual band circularly polarized (CP) rectangular loop antenna is presented. The antenna comprises two rectangular loops with parasitic rectangular elements inside the driven elements. The bandwidth is enhanced by adding parasitic elements. Antenna structure is situated above a finite ground plane. Two parasitic rectangular loops are connected by a short dipole. To get circular polarization, one gap on the longer side of each rectangular loop is introduced symmetrically with respect to the center of the structure. Each driven loop is fed through short dipole connecting two parasitic rectangular loops. One more feeding is introduced for each driven loop through finite ground plane. Antenna resonance frequency is mainly depends on the circumference of the rectangular loop. The operating bandwidth and symmetry of the pattern is mainly depends on the aspect ratio of the rectangular loop. To get good axial ratio (AR) and return loss, the position of gap and the height of the rectangular loop from the ground plane are very important. The proposed loop antenna has a impedance bandwidth at the frequency of 1.575 GHz and 2.45 GHz are 296 MHz and 600 MHz respectively. Maximum gain of around 8.9 dBi and 7.86 dBi has been achieved at the frequency of 1.575 GHz and 2.45 GHz respectively. The acceptable axial ratio value has been achieved. The proposed antenna can be used for Global Positioning System (GPS) and ISM band applications.","PeriodicalId":174192,"journal":{"name":"2015 International Conference on Communications and Signal Processing (ICCSP)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128124771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-12DOI: 10.1109/ICCSP.2015.7322573
M. Dhamodaran, R. Dhanasekaran
In this paper finite element method (FEM) has been used to obtain the accurate and efficient computation of capacitance of different conducting bodies like cylinder, cube, cone, sphere, pyramid and tetrahedron. The surfaces are discretized using triangular subsections. For each of these objects, aseries of values of the number of N segments has been used. FEM is better method than Finite Difference Method and Method of Moment as it is easy to apply to complex region and it is possible to solve different types of problem. This paper presents the results for capacitance of different conducting shapes. The obtained results are compared with previous related works. The use of FEM results in a highly accurate solutions with significant savings in computation time and memory requirements.
{"title":"Estimation of capacitance of different conducting objects using triangular subsection","authors":"M. Dhamodaran, R. Dhanasekaran","doi":"10.1109/ICCSP.2015.7322573","DOIUrl":"https://doi.org/10.1109/ICCSP.2015.7322573","url":null,"abstract":"In this paper finite element method (FEM) has been used to obtain the accurate and efficient computation of capacitance of different conducting bodies like cylinder, cube, cone, sphere, pyramid and tetrahedron. The surfaces are discretized using triangular subsections. For each of these objects, aseries of values of the number of N segments has been used. FEM is better method than Finite Difference Method and Method of Moment as it is easy to apply to complex region and it is possible to solve different types of problem. This paper presents the results for capacitance of different conducting shapes. The obtained results are compared with previous related works. The use of FEM results in a highly accurate solutions with significant savings in computation time and memory requirements.","PeriodicalId":174192,"journal":{"name":"2015 International Conference on Communications and Signal Processing (ICCSP)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125529600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-12DOI: 10.1109/ICCSP.2015.7322615
Sampaio. José, R. Itagi
This paper discusses the importance of smart grid, renewable energy sources, and schemes of implementing solar power plants in Indian scenario. The features and limitations of the two types of available solar power plants are discussed. The modifications required to make the solar plant to a smart or intelligent solar plant are suggested.
{"title":"Smart solar power plant","authors":"Sampaio. José, R. Itagi","doi":"10.1109/ICCSP.2015.7322615","DOIUrl":"https://doi.org/10.1109/ICCSP.2015.7322615","url":null,"abstract":"This paper discusses the importance of smart grid, renewable energy sources, and schemes of implementing solar power plants in Indian scenario. The features and limitations of the two types of available solar power plants are discussed. The modifications required to make the solar plant to a smart or intelligent solar plant are suggested.","PeriodicalId":174192,"journal":{"name":"2015 International Conference on Communications and Signal Processing (ICCSP)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128200620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-12DOI: 10.1109/ICCSP.2015.7322634
V. Chaudhary, I. S. Rao
This paper presents a design of a novel RF Power Amplifier which is suitable for Base stations and modern wireless communication systems. High broadband power efficiency is observed from 1.7-2.7 GHz, where PAE> 80% when we use second harmonic input tuning. The main purpose for applying second harmonic tuning circuit is to improve the switching behaviour and enhance the efficiency for a class-E power amplifier. Without any harmonic circuitry, we obtain a PAE of 77% and after optimizing the component parameter, the input and output terminals are both well matched and addition of second harmonic trap circuit improves efficiency to 81%. A new output power circuit technique is employed for proposed Power Amplifier by using combination of inductors and capacitors of different sizes. The technique involves the use to combine the output of individual Power Amplifier into an unbalance load by use of a small RF-choke in output matching circuit. The proposed Power Amplifier is simulated by using Agilent's Advanced Design System (ADS) and result shows that Power Amplifier deliver 81% efficiency with respect to input RF Power and 28dBm Output Power at 2GHz frequency. This work has the highest Efficiency among the reported work in class-E Power Amplifier design using different methods. The purpose of this paper is to demonstrate the designing of Power Amplifier and improvement in efficiency while maintaining the stability.
{"title":"A novel 2GHz highly efficiency improved class-E Power Amplifier for Base stations","authors":"V. Chaudhary, I. S. Rao","doi":"10.1109/ICCSP.2015.7322634","DOIUrl":"https://doi.org/10.1109/ICCSP.2015.7322634","url":null,"abstract":"This paper presents a design of a novel RF Power Amplifier which is suitable for Base stations and modern wireless communication systems. High broadband power efficiency is observed from 1.7-2.7 GHz, where PAE> 80% when we use second harmonic input tuning. The main purpose for applying second harmonic tuning circuit is to improve the switching behaviour and enhance the efficiency for a class-E power amplifier. Without any harmonic circuitry, we obtain a PAE of 77% and after optimizing the component parameter, the input and output terminals are both well matched and addition of second harmonic trap circuit improves efficiency to 81%. A new output power circuit technique is employed for proposed Power Amplifier by using combination of inductors and capacitors of different sizes. The technique involves the use to combine the output of individual Power Amplifier into an unbalance load by use of a small RF-choke in output matching circuit. The proposed Power Amplifier is simulated by using Agilent's Advanced Design System (ADS) and result shows that Power Amplifier deliver 81% efficiency with respect to input RF Power and 28dBm Output Power at 2GHz frequency. This work has the highest Efficiency among the reported work in class-E Power Amplifier design using different methods. The purpose of this paper is to demonstrate the designing of Power Amplifier and improvement in efficiency while maintaining the stability.","PeriodicalId":174192,"journal":{"name":"2015 International Conference on Communications and Signal Processing (ICCSP)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125109814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-12DOI: 10.1109/ICCSP.2015.7322930
A. M. Diffni Gomez, N. B. Prakash, B. Vigneshwaran
In recent years there is a need of alternative insulating fluid for replacing the transformer oil is increased. Owing to the poor biodegradability and availability, vegetable oil has widely replaced the conventional mineral oil used in power apparatus for various applications. Since field investigations may require a longtime progress for observing the aging effects of dielectric materials. In general many researches performed accelerated aging test for predicting the lifetime of liquid dielectrics in laboratory. Partial Discharge (PD) is a vital tool for investigating the insulation degradation of dielectric materials. In this paper, various insulating oil characteristics such as breakdown voltage, viscosity, flash point and fire point are obtained for virgin and thermal aged Mineral oil and Natural ester sample. The result shows that natural ester exhibit good electrical and thermal characteristics than mineral oil.
{"title":"Investigation on electrical characteristics of dielectric fluids under aging phenomena","authors":"A. M. Diffni Gomez, N. B. Prakash, B. Vigneshwaran","doi":"10.1109/ICCSP.2015.7322930","DOIUrl":"https://doi.org/10.1109/ICCSP.2015.7322930","url":null,"abstract":"In recent years there is a need of alternative insulating fluid for replacing the transformer oil is increased. Owing to the poor biodegradability and availability, vegetable oil has widely replaced the conventional mineral oil used in power apparatus for various applications. Since field investigations may require a longtime progress for observing the aging effects of dielectric materials. In general many researches performed accelerated aging test for predicting the lifetime of liquid dielectrics in laboratory. Partial Discharge (PD) is a vital tool for investigating the insulation degradation of dielectric materials. In this paper, various insulating oil characteristics such as breakdown voltage, viscosity, flash point and fire point are obtained for virgin and thermal aged Mineral oil and Natural ester sample. The result shows that natural ester exhibit good electrical and thermal characteristics than mineral oil.","PeriodicalId":174192,"journal":{"name":"2015 International Conference on Communications and Signal Processing (ICCSP)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132857899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-12DOI: 10.1109/ICCSP.2015.7322927
R. Vishnu, S. S. Anulal
Modem frequency hopping radios makes use of Direct Digital Synthesis (DDS) - Phase Locked Loop (PLL) hybrid architecture based frequency synthesizers. The advantage is the fast switching speed and fine tuning resolution of the DDS, complemented with very low phase noise and spurious performance of the PLL. Integer boundary spur is a problem area, which restrict the spurious performance of the DDS-PLL translation loop. An algorithm was developed which identifies whether the tuned frequency is prone to integer boundary spurs. If it is, then the DDS and PLL frequencies are configured such that the generated spurs are outside the loop filter bandwidth, so that they are attenuated by the loop. The algorithm runs as a sub-routine in the micro-controller which programs the DDS and PLL. This algorithm was developed and tested on a wideband frequency synthesizer operating from 600-1200MHz, albeit the method is independent of frequency of operation.
{"title":"An avoidance technique for mitigating the integer boundary spur problem in a DDS-PLL hybrid frequency synthesizer","authors":"R. Vishnu, S. S. Anulal","doi":"10.1109/ICCSP.2015.7322927","DOIUrl":"https://doi.org/10.1109/ICCSP.2015.7322927","url":null,"abstract":"Modem frequency hopping radios makes use of Direct Digital Synthesis (DDS) - Phase Locked Loop (PLL) hybrid architecture based frequency synthesizers. The advantage is the fast switching speed and fine tuning resolution of the DDS, complemented with very low phase noise and spurious performance of the PLL. Integer boundary spur is a problem area, which restrict the spurious performance of the DDS-PLL translation loop. An algorithm was developed which identifies whether the tuned frequency is prone to integer boundary spurs. If it is, then the DDS and PLL frequencies are configured such that the generated spurs are outside the loop filter bandwidth, so that they are attenuated by the loop. The algorithm runs as a sub-routine in the micro-controller which programs the DDS and PLL. This algorithm was developed and tested on a wideband frequency synthesizer operating from 600-1200MHz, albeit the method is independent of frequency of operation.","PeriodicalId":174192,"journal":{"name":"2015 International Conference on Communications and Signal Processing (ICCSP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130880381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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