{"title":"A rotationally switched rod memory with a 100-nanosecond cycle time","authors":"B. Kaufman, P. Ellinger, H. Kuno","doi":"10.1145/1464291.1464323","DOIUrl":null,"url":null,"abstract":"Thin film memory techniques are beginning to offer an attractive alternative to magnetic core memories, particularly for high-speed operation. The memory reported in this paper utilizes a plated-wire (Rod) memory device operating in a 512-word 36 bit per word memory system. The DRO mode is employed and operation at a 100-nanosecond read-write cycle time is achieved. In order to attain this high speed, modified concepts of memory circuitry have evolved affecting every aspect of the memory design. Integrated circuit techniques have been employed for all logic and sensing functions and may be utilized to break some of the economically imposed limitations on contemporary memory circuit design. The potential for low-cost batch fabrication of monolithic and hybrid circuits requires utilization of these techniques to secure cost and performance improvements. Accordingly, the design for this memory makes maximum use of the existing and projected capabilities of integrated circuits.","PeriodicalId":297471,"journal":{"name":"AFIPS '66 (Fall)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1899-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"AFIPS '66 (Fall)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1464291.1464323","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
Thin film memory techniques are beginning to offer an attractive alternative to magnetic core memories, particularly for high-speed operation. The memory reported in this paper utilizes a plated-wire (Rod) memory device operating in a 512-word 36 bit per word memory system. The DRO mode is employed and operation at a 100-nanosecond read-write cycle time is achieved. In order to attain this high speed, modified concepts of memory circuitry have evolved affecting every aspect of the memory design. Integrated circuit techniques have been employed for all logic and sensing functions and may be utilized to break some of the economically imposed limitations on contemporary memory circuit design. The potential for low-cost batch fabrication of monolithic and hybrid circuits requires utilization of these techniques to secure cost and performance improvements. Accordingly, the design for this memory makes maximum use of the existing and projected capabilities of integrated circuits.