A practical approach for the accurate lifetime estimation of device degradation in deep sub-micron CMOS technologies

Abstract

Practical studies of the influence of various reliability mechanisms on the lifetime estimation and the impact of widely accepted assumptions to the accuracy of the reliability degradation predictions are discussed in detail. The inaccuracies of the "industry standard" approach to reliability stressing as well as the methodology utilized for the prediction of lifetimes in advanced CMOS technologies are addressed. A review of measurement practices and stress conditions is also given. Methodologies for improving the accuracy of reliability predictions have been developed and validated with experimental results for devices with an L/sub EFF/ range spanning well into the deep sub-micron regime, and with stress conditions covering a wide V/sub GS/ and V/sub DS/ range. The impact of NFET and PFET reliability degradation on circuit performance has been characterized using ring oscillator stressing. The traditional view that only NFET hot carrier degradation contributes to circuit performance degradation has been shown not to be applicable for advanced sub-micron CMOS technologies. The need of a more comprehensive reliability evaluation for realistic lifetime projections is described.