Investigation and design of the efficient hardware-based RNG for cryptographic applications

Ahmad Hafiz Mohamad Razy, S. Z. M. Naziri, R. C. Ismail, N. Idris
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引用次数: 1

Abstract

The best security factor in any encryption algorithm is the random values used in key management or the structure of the algorithm itself. Thus, some of the encryption algorithm employed random number generator to produce this type of numbers. This paper describes the process of selecting the most efficient algorithm to represent the hardware RNG for the usage in cryptography. For this purpose, a number of RNG algorithms are selected and analyzed in terms of the sequence's randomness using theoretical simulator analysis. Among of the algorithms, the Inverse Congruential Generator algorithm was chosen based on the analysis as it provides the most high quality random sequence and insensitivity in initial condition. The algorithm was further proceed to the NIST test for non-randomness test and it shown reasonable complexity. The design was proven to be implemented successfully on hardware as it then been designed using Verilog HDL and been simulated and verified using Altera QuartusII 9.0sp2 web edition software. The design utilized 7,711 logic elements of Cyclone EP1C20F400C6. Benefited the usage of FPGA, the design could possibly provide reduction in size of the RNG, low power consumption and low cost production for hardware-based encryption.
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基于硬件的高效RNG密码学应用研究与设计
在任何加密算法中,最好的安全系数是密钥管理中使用的随机值或算法本身的结构。因此,有些加密算法采用随机数生成器来产生这类数字。本文描述了在密码学中选择最有效的算法来表示硬件RNG的过程。为此,选择了一些RNG算法,并使用理论模拟器分析了序列的随机性。通过分析,选择了逆同余发生器算法,该算法具有随机序列质量最高、初始条件不敏感的特点。该算法进一步进行了NIST非随机性测试,显示出合理的复杂度。采用Verilog HDL进行设计,并使用Altera QuartusII 9.0sp2网络版软件进行仿真和验证,证明了该设计在硬件上的成功实现。设计利用了Cyclone EP1C20F400C6的7711个逻辑元件。得益于FPGA的使用,该设计可能会减少RNG的尺寸,降低功耗和基于硬件的加密的低成本生产。
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