Performance Evaluation of Gate-All-Around Si Nanowire Transistors with SiGe Strain engineering

Abstract

Gate-all-around nanowire transistors show inherently best gate control which gives them an advantage for future applications, possibly below 5nm technology nodes. We investigate several critical aspects that need to be addressed for nanowire transistors to surpass current FinFETs by the introduction of process-induced stress in the channel. Using an advanced simulation framework we analyze Si nanowire transistors. We report on the characterization of strain components in the structures with silicon–germanium source-drain extension. Lattice strain analysis is performed using elasticity theory. Self-consistent Schrodinger-Poisson based simulations are used to clarify the physical mechanisms for mobility enhancement and to provide guidelines for nanowire transistor design. Finally, we investigate how the most favorable stress configurations in the channel can translate into improvements in performance metrics such as on/off current ratio, threshold voltage, and subthreshold slope of strain-engineered nanowire transistors.