A Compact and Accelerated Spike-based Neuromorphic VLSI Chip for Pattern Recognition

Abstract

In this paper, we present a compact and accelerated spike-based neuromorphic chip that support on-line pattern recognition. The chip integrates 100 input layer neurons and 7000 synaptic plasticity circuits to handle the pattern classification problem of a 10×10 input pixel array. With the mechanism of spike-timing dependent plasticity (STDP) circuits and teacher signals, the chip can support both supervised learning and unsupervised learning. Fabricated in a 55nm technology, the core circuits occupies the area of 623×540 μm2The simulation results show that the chip can handle the pattern recognition task such as MNIST data set classification, and the power consumption is about 5.5mW.