The Design of Single Chip Memory Management Unit/Data Cache

Abstract

CAM-based translation mechanism and a large instruction data cache onto a single chip (Figure 1). Thib architecture combines high performance memory management with systemlevel caching to eliminate address translation overhead, and achieves the high hit rate and functionality of a physical-based cache. Fully automatic and feature-rich memory management support, and upward protocol and O S compatibility, are provided. The chip, fabricated using AT&T's lum Twin Tub CMOS, l contains approx. 400,000 transistors and is housed in a 133 pin pin-grid-array package. Power dissipation is about 1 watt at the operating frequency of 21 MHz. The silicon is currently fully operational at 24MHz and is available in preproduction quantities.