{"title":"Low power HBC PHY baseband transceiver for IEEE 802.15.6 WBAN","authors":"Abdelhay Ali, A. Shalaby, M. Sayed, M. Abo-Zahhad","doi":"10.1109/ICM.2017.8268857","DOIUrl":null,"url":null,"abstract":"The monitoring healthcare systems that can be used by patients wherever they are, has become very important for today efficient healthcare. Wireless body area network is one possible realization of these systems. Based on IEEE 802.15.6-2012 standard, this paper proposes a low power architecture of Human Body Communication transceiver for Wireless Body Area Network. A new efficient frame synchronization algorithm based on adaptive threshold is adopted. The proposed design is coded and simulated using MATLAB software. Then, the transceiver is implemented using Verilog and synthesized to 90nm CMOS technology. The implemented architecture meets all the standard requirements, consumes 0.63mW, and operates at a clock frequency of 42MHz.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 29th International Conference on Microelectronics (ICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2017.8268857","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
The monitoring healthcare systems that can be used by patients wherever they are, has become very important for today efficient healthcare. Wireless body area network is one possible realization of these systems. Based on IEEE 802.15.6-2012 standard, this paper proposes a low power architecture of Human Body Communication transceiver for Wireless Body Area Network. A new efficient frame synchronization algorithm based on adaptive threshold is adopted. The proposed design is coded and simulated using MATLAB software. Then, the transceiver is implemented using Verilog and synthesized to 90nm CMOS technology. The implemented architecture meets all the standard requirements, consumes 0.63mW, and operates at a clock frequency of 42MHz.