AGRAS: Aging and memory request rate aware scheduler for PCM memories

N. Aswathy, H. Kapoor
{"title":"AGRAS: Aging and memory request rate aware scheduler for PCM memories","authors":"N. Aswathy, H. Kapoor","doi":"10.1109/ISQED57927.2023.10129369","DOIUrl":null,"url":null,"abstract":"Emerging non-volatile memories overcome the bottlenecks associated with traditional DRAM memories, such as low density and high energy. The high operating voltages required for such non-volatile memories make them vulnerable to Biased Temperature Instability (BTI) aging. The aging of a device can be controlled by the de-stress operation, where the stress voltage applied to the device is removed for a small duration. Performing de-stress in regular intervals helps to partially recover from age degradation. Such an interval-based de-stress can affect the service of regular requests and thus can hamper the system performance.To control the aging of PCM memories while maintaining the system performance, we propose AGRAS: age and memory request-rate aware scheduling method to schedule de-stress as well as regular requests. AGRAS schedules the de-stress operation only when the incoming request rate is not very high, thus controlling performance degradation. Additionally, it makes sure that in events of a prolonged high request rate, the de-stress gets scheduled in order to control device age degradation. The proposal helps to improve the system performance while minimizing the age degradation compared to the setup, which de-stresses at regular intervals.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 24th International Symposium on Quality Electronic Design (ISQED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED57927.2023.10129369","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

Emerging non-volatile memories overcome the bottlenecks associated with traditional DRAM memories, such as low density and high energy. The high operating voltages required for such non-volatile memories make them vulnerable to Biased Temperature Instability (BTI) aging. The aging of a device can be controlled by the de-stress operation, where the stress voltage applied to the device is removed for a small duration. Performing de-stress in regular intervals helps to partially recover from age degradation. Such an interval-based de-stress can affect the service of regular requests and thus can hamper the system performance.To control the aging of PCM memories while maintaining the system performance, we propose AGRAS: age and memory request-rate aware scheduling method to schedule de-stress as well as regular requests. AGRAS schedules the de-stress operation only when the incoming request rate is not very high, thus controlling performance degradation. Additionally, it makes sure that in events of a prolonged high request rate, the de-stress gets scheduled in order to control device age degradation. The proposal helps to improve the system performance while minimizing the age degradation compared to the setup, which de-stresses at regular intervals.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
用于PCM存储器的老化和内存请求率感知调度器
新兴的非易失性存储器克服了传统DRAM存储器的瓶颈,如低密度和高能量。这种非易失性存储器所需的高工作电压使它们容易受到偏温不稳定性(BTI)老化的影响。设备的老化可以通过去应力操作来控制,即在一小段时间内去除施加在设备上的应力电压。定期进行减压有助于从年龄退化中部分恢复。这种基于间隔的减压会影响常规请求的服务,从而影响系统性能。为了在保持系统性能的同时控制PCM存储器的老化,我们提出了AGRAS:年龄和存储器请求率感知调度方法来调度减压和常规请求。AGRAS仅在传入请求率不是很高时调度减压操作,从而控制性能下降。此外,它确保在长时间高请求率的情况下,调度减压以控制设备老化。该方案有助于提高系统性能,同时最大限度地减少与设置相比的老化,后者定期减压。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Metal Inter-layer Via Keep-out-zone in M3D IC: A Critical Process-aware Design Consideration HD2FPGA: Automated Framework for Accelerating Hyperdimensional Computing on FPGAs A Novel Stochastic LSTM Model Inspired by Quantum Machine Learning DC-Model: A New Method for Assisting the Analog Circuit Optimization Polynomial Formal Verification of a Processor: A RISC-V Case Study
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1