Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129328
Chieh-Yu Cheng, Ting-Chi Wang
Placement is a critical step in a modern physical design flow, and the routability of the placement result is a major issue that must be taken into account. In this work, we explore the possibility of using placement guidance to mitigate routing congestion and reduce design rule violations for mixed-size designs. By extracting the underlying knowledge of a mixed-size design using a graph neural network, we generate an embedding for each standard cell. Based on the embeddings, we cluster standard cells into groups and create the placement guidance. By adding the placement guidance to a commercial place-and-route tool, the tool will strive to avoid the fragmentation of standard cells with dense connections in the placement stage. Experimental results show that our placement guidance generation methodology helps the commercial tool reduce 26% routing overflow and 65% design rule violations for the test cases.
{"title":"Routability-aware Placement Guidance Generation for Mixed-size Designs","authors":"Chieh-Yu Cheng, Ting-Chi Wang","doi":"10.1109/ISQED57927.2023.10129328","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129328","url":null,"abstract":"Placement is a critical step in a modern physical design flow, and the routability of the placement result is a major issue that must be taken into account. In this work, we explore the possibility of using placement guidance to mitigate routing congestion and reduce design rule violations for mixed-size designs. By extracting the underlying knowledge of a mixed-size design using a graph neural network, we generate an embedding for each standard cell. Based on the embeddings, we cluster standard cells into groups and create the placement guidance. By adding the placement guidance to a commercial place-and-route tool, the tool will strive to avoid the fragmentation of standard cells with dense connections in the placement stage. Experimental results show that our placement guidance generation methodology helps the commercial tool reduce 26% routing overflow and 65% design rule violations for the test cases.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"2010 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127353313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Deep neural networks (DNNs) are vulnerable to adversarial inputs, which are created by adding minor perturbations to the genuine inputs. Previous gradient-based adversarial attacks, such as the "fast gradient sign method" (FGSM), add an equal amount (say ϵ) of noise to all the pixels of an image. This degrades image quality significantly, such that a human validator can easily detect the resultant adversarial samples. We propose a novel gradient-based adversarial attack technique named SpotOn, which seeks to maintain the quality of adversarial images high. We first identify an image’s region of importance (ROI) using Grad-CAM. SpotOn has three variants. Two variants of SpotOn attack only the ROI, whereas the third variant adds an epsilon (ϵ) amount of noise to the ROI and a much smaller amount of noise (say ϵ/3) to the remaining image. On Caltech101 dataset, compared to FGSM, SpotOn achieves comparable degradation in CNN accuracy while maintaining much higher image quality. For example, for ϵ = 0.1, FGSM degrades VGG19 accuracy from 92% to 8% and leads to an SSIM value of 0.48 by attacking all pixels in an image. By contrast, SpotOn-VariableNoise attacks only 34.8% of the pixels in the image; degrades accuracy to 10.5% and maintains an SSIM value of 0.78. This makes SpotOn an effective data-poisoning attack technique. The code is available from https://github.com/CandleLabAI/SpotOn-AttackOnDNNs.
{"title":"SpotOn: A Gradient-based Targeted Data Poisoning Attack on Deep Neural Networks","authors":"Yash Khare, Kumud Lakara, Sparsh Mittal, Arvind Kaushik, Rekha Singhal","doi":"10.1109/ISQED57927.2023.10129311","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129311","url":null,"abstract":"Deep neural networks (DNNs) are vulnerable to adversarial inputs, which are created by adding minor perturbations to the genuine inputs. Previous gradient-based adversarial attacks, such as the \"fast gradient sign method\" (FGSM), add an equal amount (say ϵ) of noise to all the pixels of an image. This degrades image quality significantly, such that a human validator can easily detect the resultant adversarial samples. We propose a novel gradient-based adversarial attack technique named SpotOn, which seeks to maintain the quality of adversarial images high. We first identify an image’s region of importance (ROI) using Grad-CAM. SpotOn has three variants. Two variants of SpotOn attack only the ROI, whereas the third variant adds an epsilon (ϵ) amount of noise to the ROI and a much smaller amount of noise (say ϵ/3) to the remaining image. On Caltech101 dataset, compared to FGSM, SpotOn achieves comparable degradation in CNN accuracy while maintaining much higher image quality. For example, for ϵ = 0.1, FGSM degrades VGG19 accuracy from 92% to 8% and leads to an SSIM value of 0.48 by attacking all pixels in an image. By contrast, SpotOn-VariableNoise attacks only 34.8% of the pixels in the image; degrades accuracy to 10.5% and maintains an SSIM value of 0.78. This makes SpotOn an effective data-poisoning attack technique. The code is available from https://github.com/CandleLabAI/SpotOn-AttackOnDNNs.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124857934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129393
Lakshmi Sathidevi, Abhinav Sharma, Nan Wu, Xun Jiao, Cong Hao
While Approximate Computing (AxC) is a promising technique to trade off accuracy for energy efficiency, one fundamental challenge is the lack of accurate and informative error models of AxC applications. In this work, we propose PreAxC, a novel error modeling and prediction flow for AxC designs. Instead of using simple error statistics as in existing work, we use error distribution for AxC circuit error analysis with input awareness. We propose graph neural network (GNN) based methods to predict the error distribution of AxC programs, which are represented as data flow graphs (DFGs). We propose two approaches: model-free and model-based, where the former directly predicts the error distribution histogram, and the latter models the distribution using Gaussian Mixture Model (GMM) and predicts the GMM parameters. Experiment results demonstrate that our approaches can outperform existing error statistics and can successfully predict the error distribution, especially the model-free approach, even for completely unseen graphs (representing new AxC programs) during training.
{"title":"PreAxC: Error Distribution Prediction for Approximate Computing Quality Control using Graph Neural Networks","authors":"Lakshmi Sathidevi, Abhinav Sharma, Nan Wu, Xun Jiao, Cong Hao","doi":"10.1109/ISQED57927.2023.10129393","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129393","url":null,"abstract":"While Approximate Computing (AxC) is a promising technique to trade off accuracy for energy efficiency, one fundamental challenge is the lack of accurate and informative error models of AxC applications. In this work, we propose PreAxC, a novel error modeling and prediction flow for AxC designs. Instead of using simple error statistics as in existing work, we use error distribution for AxC circuit error analysis with input awareness. We propose graph neural network (GNN) based methods to predict the error distribution of AxC programs, which are represented as data flow graphs (DFGs). We propose two approaches: model-free and model-based, where the former directly predicts the error distribution histogram, and the latter models the distribution using Gaussian Mixture Model (GMM) and predicts the GMM parameters. Experiment results demonstrate that our approaches can outperform existing error statistics and can successfully predict the error distribution, especially the model-free approach, even for completely unseen graphs (representing new AxC programs) during training.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124990895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129395
Xiaotian Ma, Jiaqi Tang, Y. Bai
As deep neural networks have continuously advanced computer version tasks, researchers from academia and industry focus on developing a powerful deep neural network model to process volumes of data. With the increasing size of DNN models, their inference process is computationally expensive and limits the employment of DNNs in real-time applications.In response, we present the proposed Locality-sensing Fast Neural Network (LFNN), a generalized framework for accelerating the querying videos process via locality sensing to reduce the cost of DNN in video evaluation by three times saving in inference time. The LFNN framework can automatically sense the similarity between two input frames via a defined locality from a given input video. The LFNN framework enables us to process the input videos within the specialized processing method that is far less computationally expensive than conventional DNN inference that conducts detection for each frame. Within the highlighted temporal locality information across frames, the Yolov5 algorithm can be accelerated by two to three times. Experimental results show that the proposed LFNN is easily implemented on the FPGA board with neglectable extra hardware costs.
{"title":"Locality-sensing Fast Neural Network (LFNN): An Efficient Neural Network Acceleration Framework via Locality Sensing for Real-time Videos Queries","authors":"Xiaotian Ma, Jiaqi Tang, Y. Bai","doi":"10.1109/ISQED57927.2023.10129395","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129395","url":null,"abstract":"As deep neural networks have continuously advanced computer version tasks, researchers from academia and industry focus on developing a powerful deep neural network model to process volumes of data. With the increasing size of DNN models, their inference process is computationally expensive and limits the employment of DNNs in real-time applications.In response, we present the proposed Locality-sensing Fast Neural Network (LFNN), a generalized framework for accelerating the querying videos process via locality sensing to reduce the cost of DNN in video evaluation by three times saving in inference time. The LFNN framework can automatically sense the similarity between two input frames via a defined locality from a given input video. The LFNN framework enables us to process the input videos within the specialized processing method that is far less computationally expensive than conventional DNN inference that conducts detection for each frame. Within the highlighted temporal locality information across frames, the Yolov5 algorithm can be accelerated by two to three times. Experimental results show that the proposed LFNN is easily implemented on the FPGA board with neglectable extra hardware costs.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129945612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129388
Ananya Mantravadi, Dhruv Makwana, R. S. Teja, Sparsh Mittal, Rekha Singhal
The rapid growth in the volume and complexity of PCB design has encouraged researchers to explore automatic visual inspection of PCB components. Automatic identification of PCB components such as resistors, transistors, etc., can provide several benefits, such as producing a bill of materials, defect detection, and e-waste recycling. Yet, visual identification of PCB components is challenging since PCB components have different shapes, sizes, and colors depending on the material used and the functionality.The paper proposes a lightweight and novel neural network, Dilated Involutional Pyramid Network (DInPNet), for the classification of PCB components on the FICS-PCB dataset. DInPNet makes use of involutions superseding convolutions that possess inverse characteristics of convolutions that are location- specific and channel-agnostic. We introduce the dilated involutional pyramid (DInP) block, which consists of an involution for transforming the input feature map into a low-dimensional space for reduced computational cost, followed by a pairwise pyramidal fusion of dilated involutions that resample back the feature map. This enables learning representations for a large effective receptive field while at the same time bringing down the number of parameters considerably. DInPNet with a total of 531,485 parameters achieves 95.48% precision, 95.65% recall, and 92.59% MCC (Matthew’s correlation coefficient). To our knowledge, we are the first to use involution for performing PCB components classification. The code is released at https://github.com/CandleLabAI/DInPNet-PCB-Component-Classification.
{"title":"Dilated Involutional Pyramid Network (DInPNet): A Novel Model for Printed Circuit Board (PCB) Components Classification","authors":"Ananya Mantravadi, Dhruv Makwana, R. S. Teja, Sparsh Mittal, Rekha Singhal","doi":"10.1109/ISQED57927.2023.10129388","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129388","url":null,"abstract":"The rapid growth in the volume and complexity of PCB design has encouraged researchers to explore automatic visual inspection of PCB components. Automatic identification of PCB components such as resistors, transistors, etc., can provide several benefits, such as producing a bill of materials, defect detection, and e-waste recycling. Yet, visual identification of PCB components is challenging since PCB components have different shapes, sizes, and colors depending on the material used and the functionality.The paper proposes a lightweight and novel neural network, Dilated Involutional Pyramid Network (DInPNet), for the classification of PCB components on the FICS-PCB dataset. DInPNet makes use of involutions superseding convolutions that possess inverse characteristics of convolutions that are location- specific and channel-agnostic. We introduce the dilated involutional pyramid (DInP) block, which consists of an involution for transforming the input feature map into a low-dimensional space for reduced computational cost, followed by a pairwise pyramidal fusion of dilated involutions that resample back the feature map. This enables learning representations for a large effective receptive field while at the same time bringing down the number of parameters considerably. DInPNet with a total of 531,485 parameters achieves 95.48% precision, 95.65% recall, and 92.59% MCC (Matthew’s correlation coefficient). To our knowledge, we are the first to use involution for performing PCB components classification. The code is released at https://github.com/CandleLabAI/DInPNet-PCB-Component-Classification.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123976189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129348
Z. He, H. Sayadi
Healthcare systems have recently utilized the Internet of Medical Things (IoMT) to assist intelligent data collection and decision-making. However, the volume of malicious threats, particularly new variants of malware attacks to the connected medical devices and their connected system, has risen significantly in recent years, which poses a critical threat to patients’ confidential data and the safety of the healthcare systems. To address the high complexity of conventional software-based detection techniques, Hardware-supported Malware Detection (HMD) has proved to be efficient for detecting malware at the processors’ micro-architecture level with the aid of Machine Learning (ML) techniques applied to Hardware Performance Counter (HPC) data. In this work, we examine the suitability of various standard ML classifiers for zero-day malware detection on new data streams in the real-world operation of IoMT devices and demonstrate that such methods are not capable of detecting unknown malware signatures with a high detection rate. In response, we propose a hybrid and adaptive image-based framework based on Deep Learning and Deep Reinforcement Learning (DRL) for online hardware-assisted zero-day malware detection in IoMT devices. Our proposed method dynamically selects the best DNN-based malware detector at run-time customized for each device from a pool of highly efficient models continuously trained on all stream data. It first converts tabular hardware-based data (HPC events) into small-size images and then leverages a transfer learning technique to retrain and enhance the Deep Neural Network (DNN) based model’s performance for unknown malware detection. Multiple DNN models are trained on various stream data continuously to form an inclusive model pool. Next, a DRL-based agent constructed with two Multi-Layer Perceptrons (MLPs) is trained (one acts as an Actor and another acts as a Critic) to align the decision of selecting the most optimal DNN model for highly accurate zero-day malware detection at run-time using a limited number of hardware events. The experimental results demonstrate that our proposed AI-enabled method achieves 99% detection rate in both F1-score and AUC, with only 0.01% false positive rate and 1% false negative rate.
{"title":"Image-Based Zero-Day Malware Detection in IoMT Devices: A Hybrid AI-Enabled Method","authors":"Z. He, H. Sayadi","doi":"10.1109/ISQED57927.2023.10129348","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129348","url":null,"abstract":"Healthcare systems have recently utilized the Internet of Medical Things (IoMT) to assist intelligent data collection and decision-making. However, the volume of malicious threats, particularly new variants of malware attacks to the connected medical devices and their connected system, has risen significantly in recent years, which poses a critical threat to patients’ confidential data and the safety of the healthcare systems. To address the high complexity of conventional software-based detection techniques, Hardware-supported Malware Detection (HMD) has proved to be efficient for detecting malware at the processors’ micro-architecture level with the aid of Machine Learning (ML) techniques applied to Hardware Performance Counter (HPC) data. In this work, we examine the suitability of various standard ML classifiers for zero-day malware detection on new data streams in the real-world operation of IoMT devices and demonstrate that such methods are not capable of detecting unknown malware signatures with a high detection rate. In response, we propose a hybrid and adaptive image-based framework based on Deep Learning and Deep Reinforcement Learning (DRL) for online hardware-assisted zero-day malware detection in IoMT devices. Our proposed method dynamically selects the best DNN-based malware detector at run-time customized for each device from a pool of highly efficient models continuously trained on all stream data. It first converts tabular hardware-based data (HPC events) into small-size images and then leverages a transfer learning technique to retrain and enhance the Deep Neural Network (DNN) based model’s performance for unknown malware detection. Multiple DNN models are trained on various stream data continuously to form an inclusive model pool. Next, a DRL-based agent constructed with two Multi-Layer Perceptrons (MLPs) is trained (one acts as an Actor and another acts as a Critic) to align the decision of selecting the most optimal DNN model for highly accurate zero-day malware detection at run-time using a limited number of hardware events. The experimental results demonstrate that our proposed AI-enabled method achieves 99% detection rate in both F1-score and AUC, with only 0.01% false positive rate and 1% false negative rate.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120850113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129302
Mengxin Zheng, Fan Chen, Lei Jiang, Qian Lou
The widespread use of machine learning is changing our daily lives. Unfortunately, clients are often concerned about the privacy of their data when using machine learning-based applications. To address these concerns, the development of privacy-preserving machine learning (PPML) is essential. One promising approach is the use of fully homomorphic encryption (FHE) based PPML, which enables services to be performed on encrypted data without decryption. Although the speed of computationally expensive FHE operations can be significantly boosted by prior ASIC-based FHE accelerators, the performance of key-switching, the dominate primitive in various FHE operations, is seriously limited by their small bit-width datapaths and frequent matrix transpositions. In this paper, we present an electro-optical (EO) PPML accelerator, PriML, to accelerate FHE operations. Its 512-bit datapath supporting 510-bit residues greatly reduces the key-switching cost. We also create an in-scratchpad-memory transpose unit to fast transpose matrices. Compared to prior PPML accelerators, on average, PriML reduces the latency of various machine learning applications by > 94.4% and the energy consumption by > 95%.
{"title":"PriML: An Electro-Optical Accelerator for Private Machine Learning on Encrypted Data","authors":"Mengxin Zheng, Fan Chen, Lei Jiang, Qian Lou","doi":"10.1109/ISQED57927.2023.10129302","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129302","url":null,"abstract":"The widespread use of machine learning is changing our daily lives. Unfortunately, clients are often concerned about the privacy of their data when using machine learning-based applications. To address these concerns, the development of privacy-preserving machine learning (PPML) is essential. One promising approach is the use of fully homomorphic encryption (FHE) based PPML, which enables services to be performed on encrypted data without decryption. Although the speed of computationally expensive FHE operations can be significantly boosted by prior ASIC-based FHE accelerators, the performance of key-switching, the dominate primitive in various FHE operations, is seriously limited by their small bit-width datapaths and frequent matrix transpositions. In this paper, we present an electro-optical (EO) PPML accelerator, PriML, to accelerate FHE operations. Its 512-bit datapath supporting 510-bit residues greatly reduces the key-switching cost. We also create an in-scratchpad-memory transpose unit to fast transpose matrices. Compared to prior PPML accelerators, on average, PriML reduces the latency of various machine learning applications by > 94.4% and the energy consumption by > 95%.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126070431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129300
Chia-Heng Yen, Jung-Che Tsai, Kai-Chiang Wu
As the outsourcing process in the design and fabrication to third parties becomes more popular in the IC industry, the consciousness of hardware security has been rising these years. In this paper, we propose a novel method for hardware Trojan detection using specific path features at the gate level. In the training flow, path classifiers can be trained with SVM and RF algorithms using the path features from the trained circuits. In the classifying flow, an average of 0.96 on the F1-score in the results of the path classification demonstrates that logical paths can be easily classified into Trojan paths and Trojan-free paths with the trained path classifiers. In the localizing flow, the intersections between the logical paths can be favorable for precisely localizing the Trojan gates. As the FPRs are kept low to prevent normal gates from misclassifying into the Trojan gates, the high TPRs can be obtained for localizing the Trojan gates with the proposed scoring method.
{"title":"Using Path Features for Hardware Trojan Detection Based on Machine Learning Techniques","authors":"Chia-Heng Yen, Jung-Che Tsai, Kai-Chiang Wu","doi":"10.1109/ISQED57927.2023.10129300","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129300","url":null,"abstract":"As the outsourcing process in the design and fabrication to third parties becomes more popular in the IC industry, the consciousness of hardware security has been rising these years. In this paper, we propose a novel method for hardware Trojan detection using specific path features at the gate level. In the training flow, path classifiers can be trained with SVM and RF algorithms using the path features from the trained circuits. In the classifying flow, an average of 0.96 on the F1-score in the results of the path classification demonstrates that logical paths can be easily classified into Trojan paths and Trojan-free paths with the trained path classifiers. In the localizing flow, the intersections between the logical paths can be favorable for precisely localizing the Trojan gates. As the FPRs are kept low to prevent normal gates from misclassifying into the Trojan gates, the high TPRs can be obtained for localizing the Trojan gates with the proposed scoring method.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132798597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129391
S. Kola, Yiming Li, Min-Hui Chuang
We study the variability of vertically stacked gate-all-around silicon nanosheet (GAA Si NS) complementary field-effect transistors (CFETs). The process variation effect (PVE), the work function fluctuation (WKF), and the random dopant fluctuation (RDF) of CFETs are statistically estimated using an experimentally validated device simulation technique. Among five factors of PVE, the channel thickness (TNch/TPch), the channel width (Wch), and the gate length (LG) are significant. Owing to superior GAA channel control and increased effective gate area, both WKF and RDF are suppressed. Notably, the PVE on both N-/P-FETs of GAA Si CFET induce the largest off-state current fluctuations of 80% and 278%, respectively, because the device characteristic is very sensitive to the layer thickness and width of channel.
研究了垂直堆叠栅极全硅纳米片互补场效应晶体管(cfet)的可变性。利用实验验证的器件仿真技术，统计估计了cfet的工艺变化效应(PVE)、功函数波动(WKF)和随机掺杂波动(RDF)。在PVE的5个影响因素中，通道厚度(TNch/TPch)、通道宽度(Wch)和栅极长度(LG)影响显著。由于优越的GAA通道控制和增加的有效栅极面积，WKF和RDF都被抑制。值得注意的是，由于器件特性对沟道的层厚和宽度非常敏感，GAA Si fet的N-/ p - fet上的PVE分别诱导最大的失态电流波动为80%和278%。
{"title":"Intrinsic Parameter Fluctuation and Process Variation Effect of Vertically Stacked Silicon Nanosheet Complementary Field-Effect Transistors","authors":"S. Kola, Yiming Li, Min-Hui Chuang","doi":"10.1109/ISQED57927.2023.10129391","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129391","url":null,"abstract":"We study the variability of vertically stacked gate-all-around silicon nanosheet (GAA Si NS) complementary field-effect transistors (CFETs). The process variation effect (PVE), the work function fluctuation (WKF), and the random dopant fluctuation (RDF) of CFETs are statistically estimated using an experimentally validated device simulation technique. Among five factors of PVE, the channel thickness (TNch/TPch), the channel width (Wch), and the gate length (LG) are significant. Owing to superior GAA channel control and increased effective gate area, both WKF and RDF are suppressed. Notably, the PVE on both N-/P-FETs of GAA Si CFET induce the largest off-state current fluctuations of 80% and 278%, respectively, because the device characteristic is very sensitive to the layer thickness and width of channel.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130800956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129287
J. Yin, M. Stan
Dynamic leakage suppression (DLS) technique has been investigated to suppress the static leakages of static random-access memory (SRAM) cells, but most of the related works focused on implementing the technique only on part of the circuit, leaving room for further improvements to reduce leakage. In this paper, the feed-forward DLS technique is used to construct a low leakage read buffer (RB). The DLS RB is then integrated with DLS cross-coupled inverters as a full DLS SRAM cell. From SPICE simulations based on a commercial 65nm CMOS technology, the proposed DLS RB and DLS SRAM cell with the DLS RB help reduce the leakage power by 73.96% and 49.84%, respectively, compared to the corresponding 4T RB and DLS SRAM cell with the 4T RB. Additionally, a DLS "pseudo-device" is proposed to optimize parameters of transistors and the trade-off between leakage and performance. Lastly, a DLS SRAM array macro using the proposed DLS SRAM cell achieves a maximum operating frequency of 10.9kHz at the minimum operating voltage of 0.4V and a total leakage current of 2.15nA (leakage power of 645fW) scaled up to 4kb at 0.3V suitable for low power data storage at Internet of Things (IoT) nodes.
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