A statistical model for path delay faults in VLSI circuits

Abstract

Faults in digital circuits are primarily the results of various random defects which can occur during manufacturing. These random defects can introduce DC (stuck-at) faults as well as AC (delay) faults. Previous work on statistical modeling and analysis for delay fault testing assumes that at most a single delay fault can occur along any given path in the circuit under test. In this paper, we study the statistical effect of multiple delay faults along any path in the circuit under test. We present a statistical model for path delay faults in VLSI circuits which takes into account multiple delay faults occurring along any given signal. We also show how to compute path delay fault probabilities for all paths in a given circuit. Furthermore, we describe how this statistical model could be used to predict important information such as the maximum number of path delay faults in a given circuit.