Pub Date : 1996-04-11DOI: 10.1109/SECON.1996.510096
M. Hamad, D. Landis
Faults in digital circuits are primarily the results of various random defects which can occur during manufacturing. These random defects can introduce DC (stuck-at) faults as well as AC (delay) faults. Previous work on statistical modeling and analysis for delay fault testing assumes that at most a single delay fault can occur along any given path in the circuit under test. In this paper, we study the statistical effect of multiple delay faults along any path in the circuit under test. We present a statistical model for path delay faults in VLSI circuits which takes into account multiple delay faults occurring along any given signal. We also show how to compute path delay fault probabilities for all paths in a given circuit. Furthermore, we describe how this statistical model could be used to predict important information such as the maximum number of path delay faults in a given circuit.
{"title":"A statistical model for path delay faults in VLSI circuits","authors":"M. Hamad, D. Landis","doi":"10.1109/SECON.1996.510096","DOIUrl":"https://doi.org/10.1109/SECON.1996.510096","url":null,"abstract":"Faults in digital circuits are primarily the results of various random defects which can occur during manufacturing. These random defects can introduce DC (stuck-at) faults as well as AC (delay) faults. Previous work on statistical modeling and analysis for delay fault testing assumes that at most a single delay fault can occur along any given path in the circuit under test. In this paper, we study the statistical effect of multiple delay faults along any path in the circuit under test. We present a statistical model for path delay faults in VLSI circuits which takes into account multiple delay faults occurring along any given signal. We also show how to compute path delay fault probabilities for all paths in a given circuit. Furthermore, we describe how this statistical model could be used to predict important information such as the maximum number of path delay faults in a given circuit.","PeriodicalId":338029,"journal":{"name":"Proceedings of SOUTHEASTCON '96","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115735359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-04-11DOI: 10.1109/SECON.1996.510057
M. A. Marra, B. Boling, B. Walcott
This study presents a method of adaptive system control based on genetic algorithms. The method consists of a population of controllers evolving towards an optimum controller through the use of probabilistic genetic operators. A brief overview of genetic algorithms is first given. The remainder of the paper identifies the problems associated with genetic algorithm controllers, and addresses the key issue of stability. A theoretical analysis of the proposed genetic algorithm controller shows that the population converges to stable controllers under fitness-proportionate selection pressure. The minimization of the effects of instability is also discussed.
{"title":"Stability analysis of genetic algorithm controllers","authors":"M. A. Marra, B. Boling, B. Walcott","doi":"10.1109/SECON.1996.510057","DOIUrl":"https://doi.org/10.1109/SECON.1996.510057","url":null,"abstract":"This study presents a method of adaptive system control based on genetic algorithms. The method consists of a population of controllers evolving towards an optimum controller through the use of probabilistic genetic operators. A brief overview of genetic algorithms is first given. The remainder of the paper identifies the problems associated with genetic algorithm controllers, and addresses the key issue of stability. A theoretical analysis of the proposed genetic algorithm controller shows that the population converges to stable controllers under fitness-proportionate selection pressure. The minimization of the effects of instability is also discussed.","PeriodicalId":338029,"journal":{"name":"Proceedings of SOUTHEASTCON '96","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116694596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-04-11DOI: 10.1109/SECON.1996.510130
M. Dabdoub, S. Wunnava
There have been several digital systems simulation software and hardware definition language (HDL) packages in use. However, most of them do not follow set standards and some of them are incremental. There has been growing interest in the VHDL (very high speed integrated circuit HDL) design platform with capabilities to design and simulate the sub-modules, then integrate them and study the response of the system as a whole. In addition VHDL has been following the standards set by the IEEE and leading industries. At Florida International University, the authors have found extensive use of the VHDL in the instructional and research disciplines in designing, simulating, and studying the responses for improved design of very complex digital systems. The authors have devised a methodology to make the VHDL, a real design and guiding tool for almost any type of digital system. They describe the educational and industrial use of VHDL specific case studies. A sequential approach to solving the design problems is presented.
目前已有几种数字系统仿真软件和硬件定义语言(HDL)包在使用。然而，他们中的大多数并不遵循既定的标准，有些是增量的。VHDL (very high speed integrated circuit HDL，超高速集成电路)设计平台具有设计和仿真子模块，然后将它们集成并研究整个系统响应的能力，因此越来越受到人们的关注。此外，VHDL一直遵循IEEE和领先行业制定的标准。在佛罗里达国际大学，作者发现VHDL在设计、模拟和研究非常复杂的数字系统改进设计的响应的教学和研究学科中得到了广泛的应用。作者设计了一种方法，使VHDL成为几乎任何类型的数字系统的真正设计和指导工具。他们描述了VHDL的教育和工业应用的具体案例研究。提出了一种解决设计问题的顺序方法。
{"title":"VHDL: a powerful digital design and simulation tool","authors":"M. Dabdoub, S. Wunnava","doi":"10.1109/SECON.1996.510130","DOIUrl":"https://doi.org/10.1109/SECON.1996.510130","url":null,"abstract":"There have been several digital systems simulation software and hardware definition language (HDL) packages in use. However, most of them do not follow set standards and some of them are incremental. There has been growing interest in the VHDL (very high speed integrated circuit HDL) design platform with capabilities to design and simulate the sub-modules, then integrate them and study the response of the system as a whole. In addition VHDL has been following the standards set by the IEEE and leading industries. At Florida International University, the authors have found extensive use of the VHDL in the instructional and research disciplines in designing, simulating, and studying the responses for improved design of very complex digital systems. The authors have devised a methodology to make the VHDL, a real design and guiding tool for almost any type of digital system. They describe the educational and industrial use of VHDL specific case studies. A sequential approach to solving the design problems is presented.","PeriodicalId":338029,"journal":{"name":"Proceedings of SOUTHEASTCON '96","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127303305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-04-11DOI: 10.1109/SECON.1996.510120
J.B. Richardson, J. Gowdy
The purpose of this paper is to develop a speech enhancement algorithm to reduce unwanted noise in a speech signal. The output of this enhancement system is a linear combination of the actual speech input to the system and a synthesized speech signal. The synthesized signal is generated using the LP coefficients and an estimate of the excitation from the current speech. The mechanical sound of the LP signal is further reduced by using an excitation signal based on the actual human excitation, not an artificially generated signal. This algorithm attempts to improve speech quality by emphasizing the speech signal rather than removing the background noise. The goal of the algorithm is to produce enhanced speech at telecommunications quality with little computational overhead.
{"title":"LPC-synthesis mixture: a low computational cost speech enhancement algorithm","authors":"J.B. Richardson, J. Gowdy","doi":"10.1109/SECON.1996.510120","DOIUrl":"https://doi.org/10.1109/SECON.1996.510120","url":null,"abstract":"The purpose of this paper is to develop a speech enhancement algorithm to reduce unwanted noise in a speech signal. The output of this enhancement system is a linear combination of the actual speech input to the system and a synthesized speech signal. The synthesized signal is generated using the LP coefficients and an estimate of the excitation from the current speech. The mechanical sound of the LP signal is further reduced by using an excitation signal based on the actual human excitation, not an artificially generated signal. This algorithm attempts to improve speech quality by emphasizing the speech signal rather than removing the background noise. The goal of the algorithm is to produce enhanced speech at telecommunications quality with little computational overhead.","PeriodicalId":338029,"journal":{"name":"Proceedings of SOUTHEASTCON '96","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122409723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-04-11DOI: 10.1109/SECON.1996.510027
M. F. Watson, D.L. Smith
An interactive computer program has been developed that assists with the coordination of overcurrent protection devices. An engineer can enter relay or fuse settings, view the resulting characteristic curves on the computer's graphical display, evaluate the coordination of the overcurrent protection devices, and save the data used for both the protection devices and the substation. The program runs on an IBM PC/AT or compatible computer with a VGA interface, but was written in the C programming language so that it could easily be recompiled for another machine.
{"title":"Graphical coordination of overcurrent protection devices using a desktop computer","authors":"M. F. Watson, D.L. Smith","doi":"10.1109/SECON.1996.510027","DOIUrl":"https://doi.org/10.1109/SECON.1996.510027","url":null,"abstract":"An interactive computer program has been developed that assists with the coordination of overcurrent protection devices. An engineer can enter relay or fuse settings, view the resulting characteristic curves on the computer's graphical display, evaluate the coordination of the overcurrent protection devices, and save the data used for both the protection devices and the substation. The program runs on an IBM PC/AT or compatible computer with a VGA interface, but was written in the C programming language so that it could easily be recompiled for another machine.","PeriodicalId":338029,"journal":{"name":"Proceedings of SOUTHEASTCON '96","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128339009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-04-11DOI: 10.1109/SECON.1996.510053
Seungug Koh, Lun Ye
The improved communication delay and connectivity using optical fiber-based interconnection links indicate that more computer systems and communication networks will use optoelectronic interconnection in the near future. However complex optoelectronic interconnect systems of today are not well supported for modeling, simulation, or synthesis. To implement successful optical links there is a need for a new CAD tool capable of simulating the behaviour of optoelectronic devices and circuits simultaneously and at multiple levels of abstraction. We introduce a VHDL-based "optoelectronic system simulator (OSS)" which can simulate electronic and photonic systems concurrently and seamlessly, with simulation examples of global signal distribution network and wavelength division multiplexed (WDM) optical links.
{"title":"Optical link simulation using VHDL","authors":"Seungug Koh, Lun Ye","doi":"10.1109/SECON.1996.510053","DOIUrl":"https://doi.org/10.1109/SECON.1996.510053","url":null,"abstract":"The improved communication delay and connectivity using optical fiber-based interconnection links indicate that more computer systems and communication networks will use optoelectronic interconnection in the near future. However complex optoelectronic interconnect systems of today are not well supported for modeling, simulation, or synthesis. To implement successful optical links there is a need for a new CAD tool capable of simulating the behaviour of optoelectronic devices and circuits simultaneously and at multiple levels of abstraction. We introduce a VHDL-based \"optoelectronic system simulator (OSS)\" which can simulate electronic and photonic systems concurrently and seamlessly, with simulation examples of global signal distribution network and wavelength division multiplexed (WDM) optical links.","PeriodicalId":338029,"journal":{"name":"Proceedings of SOUTHEASTCON '96","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124679396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-04-11DOI: 10.1109/SECON.1996.510137
Varaprasad Ballingam, Ken Christensen, F. Noel
Local area network (LAN) switches are increasingly being used to subdivide large LAN segments into multiple connected LAN "microsegments". A LAN switch is similar to a LAN bridge, but is typically higher in performance and has more ports. Communication between stations on different segments is through the LAN switch. A performance analysis is presented for a token ring LAN switch for the class of protocols known as request-response protocols. Request-response protocols are typical of many client/server applications including transaction processing. A performance model based on a detailed accounting of network delay components is presented. The performance model quantifies the importance of minimizing latency within a LAN switch. Two LAN switch frame forwarding architectures are described and evaluated. The architectures are store-and-forward and cut-through frame forwarding. The performance model demonstrates that the benefits of low delay in cut-through switching extend even to situations where attached token ring segments have a very high utilization.
{"title":"Analysis of client/server transaction delay through a local area network switch","authors":"Varaprasad Ballingam, Ken Christensen, F. Noel","doi":"10.1109/SECON.1996.510137","DOIUrl":"https://doi.org/10.1109/SECON.1996.510137","url":null,"abstract":"Local area network (LAN) switches are increasingly being used to subdivide large LAN segments into multiple connected LAN \"microsegments\". A LAN switch is similar to a LAN bridge, but is typically higher in performance and has more ports. Communication between stations on different segments is through the LAN switch. A performance analysis is presented for a token ring LAN switch for the class of protocols known as request-response protocols. Request-response protocols are typical of many client/server applications including transaction processing. A performance model based on a detailed accounting of network delay components is presented. The performance model quantifies the importance of minimizing latency within a LAN switch. Two LAN switch frame forwarding architectures are described and evaluated. The architectures are store-and-forward and cut-through frame forwarding. The performance model demonstrates that the benefits of low delay in cut-through switching extend even to situations where attached token ring segments have a very high utilization.","PeriodicalId":338029,"journal":{"name":"Proceedings of SOUTHEASTCON '96","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123355812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-04-11DOI: 10.1109/SECON.1996.510122
R. Crowley, R. Hayden, C. Uber
E-Systems, ECI Division under contract from NASA JPL, has designed the scatterometer electronics subsystem (SES) component of the SeaWinds scatterometer. The scatterometer transmits a variable width MSK modulated pulse at a nominal pulse repetition interval (PRI) of 200 Hz. Two beams are transmitted spatially orthogonal to each other, and each beams return power is measured to determine wind speed and direction at the ocean surface. Designing for the harsh environment of space presents special difficulties. This paper describes the design implementation of the signal processing circuits in the SES, with reliability requirements for space as the major design driver. Issues discussed include parts selection (radiation, derating for space, power consumption, packaging), worst case analysis, radiation issues, and design architectures to mitigate the effects of random circuit disruptions.
{"title":"Implementation of signal processing techniques in a space based scatterometer","authors":"R. Crowley, R. Hayden, C. Uber","doi":"10.1109/SECON.1996.510122","DOIUrl":"https://doi.org/10.1109/SECON.1996.510122","url":null,"abstract":"E-Systems, ECI Division under contract from NASA JPL, has designed the scatterometer electronics subsystem (SES) component of the SeaWinds scatterometer. The scatterometer transmits a variable width MSK modulated pulse at a nominal pulse repetition interval (PRI) of 200 Hz. Two beams are transmitted spatially orthogonal to each other, and each beams return power is measured to determine wind speed and direction at the ocean surface. Designing for the harsh environment of space presents special difficulties. This paper describes the design implementation of the signal processing circuits in the SES, with reliability requirements for space as the major design driver. Issues discussed include parts selection (radiation, derating for space, power consumption, packaging), worst case analysis, radiation issues, and design architectures to mitigate the effects of random circuit disruptions.","PeriodicalId":338029,"journal":{"name":"Proceedings of SOUTHEASTCON '96","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123384511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-04-11DOI: 10.1109/SECON.1996.510062
A. Almulhem, F. El-Guibaly, T. Gulliver
Congestion in ATM communications is a significant issue as it can have a dramatic effect on critical or real-time data. Forward error correction (FEC) can be used to decrease or eliminate this effect. Conventional FEC has a uniform error correction capability, which can result in poor bandwidth utilization. Adaptive FEC is more suitable because it allows a different quality of service for each data type. In this paper a versatile adaptive FEC technique is proposed. It is shown that this technique can decrease the effect of congestion and increase the channel utilization.
{"title":"Adaptive error correction for ATM communications using Reed-Solomon codes","authors":"A. Almulhem, F. El-Guibaly, T. Gulliver","doi":"10.1109/SECON.1996.510062","DOIUrl":"https://doi.org/10.1109/SECON.1996.510062","url":null,"abstract":"Congestion in ATM communications is a significant issue as it can have a dramatic effect on critical or real-time data. Forward error correction (FEC) can be used to decrease or eliminate this effect. Conventional FEC has a uniform error correction capability, which can result in poor bandwidth utilization. Adaptive FEC is more suitable because it allows a different quality of service for each data type. In this paper a versatile adaptive FEC technique is proposed. It is shown that this technique can decrease the effect of congestion and increase the channel utilization.","PeriodicalId":338029,"journal":{"name":"Proceedings of SOUTHEASTCON '96","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121267184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-04-11DOI: 10.1109/SECON.1996.510155
K. Sundaram, A. Khan
Zinc oxide-silicon heterojunctions were fabricated using both n- and p-type silicon. The zinc oxide films were deposited by magnetron sputtering process at various substrate temperatures to form these devices. The electrical properties of these devices were measured and the work function of the zinc oxide was evaluated.
{"title":"Work function determination of zinc oxide films","authors":"K. Sundaram, A. Khan","doi":"10.1109/SECON.1996.510155","DOIUrl":"https://doi.org/10.1109/SECON.1996.510155","url":null,"abstract":"Zinc oxide-silicon heterojunctions were fabricated using both n- and p-type silicon. The zinc oxide films were deposited by magnetron sputtering process at various substrate temperatures to form these devices. The electrical properties of these devices were measured and the work function of the zinc oxide was evaluated.","PeriodicalId":338029,"journal":{"name":"Proceedings of SOUTHEASTCON '96","volume":"11 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114193301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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