Enhanced gain, low voltage, rail-to-rail buffer amplifier suitable for energy harvesting

Ali Far
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引用次数: 4

Abstract

A CMOS subthreshold rail-to-rail input-output buffer amplifier suitable for energy harvesting applications is presented, having high gain (AV) of ∼ 130dB, consuming ultra low currents (IDD) of ∼ 150nA, and operating with low power supply voltage (VDD) > ∼ 0.8v. Contributions of this work are the synthesis of the following attributes: First, using a single transistor, the amplifier input stage's tail current is steered between the two PMOSFET input pairs, while one of the PMOSFET pairs is level shifted by a pair of NMOSFET source followers, which keeps the amplifier's input stage transconductance (gm) roughly constant while the inputs span rail-to-rail. Second, to boost folded cascode transconductance amplifier's (FCTA) AV, the proposed plurality of regulated cascode (RGC) current mirrors (CM) utilize a small size auxiliary amplifier, containing the same type and un-scaled FETs as that of the cascoded CMs employed within the FCTA. As such, the boosting of AV is less impeded by the otherwise higher impedance and high capacitance associated with scaled FETs, utilized in most prior art, in the RGC's auxiliary amplifier's signal path. Moreover, the RGC-CM utilizing the same FET, as that of the FCTA's CM, provides more consistency in FCTA's DC, AC, and dynamic response over process and operating condition variations. Third, a buffer driver containing a Minimum Current Selector (MCS) and an inverting current mirror amplifier (ICMA) controls the quiescent current of the inactive output transistors (FETs), while a complementary noninverting current mirror (CNICM) curbs the current waste attributed to monitoring the FET's (external load) currents. The output buffer driver is inherently fast and can work at low VDD, since it operates mainly in current mode. Montecarlo (MC) and worst case (WC) simulations indicate the following specifications are achievable: input voltage range rail to rail; output voltage range ∼ 10mV from the rails; resistive load (RL) 5K ohms capability; unity gain frequency (fu) ∼ 200KHz and phase margin (PM) ∼ 40 degrees; power supply rejection ratio (PSRR) ∼ −90dB; common mode rejection ratio (CMRR) ∼ −110dB; slew rate (SR) ∼ 3V/ 10uS; settling time (ts) ∼ 15uS; size ∼130um/side.
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增益增强,低电压,轨对轨缓冲放大器适合能量收集
提出了一种适用于能量收集应用的CMOS亚阈值轨对轨输入输出缓冲放大器,具有~ 130dB的高增益(AV)、~ 150nA的超低电流(IDD)和> ~ 0.8v的低电源电压(VDD)。这项工作的贡献是以下属性的综合:首先,使用单个晶体管,放大器输入级的尾电流在两个PMOSFET输入对之间被引导,而其中一个PMOSFET对被一对NMOSFET源跟随器电平移位,这使得放大器的输入级跨导(gm)大致恒定,而输入跨轨。其次,为了提高折叠级联码跨导放大器(FCTA)的AV,所提出的多个调节级联码(RGC)电流镜(CM)利用一个小尺寸的辅助放大器,包含与FCTA内使用的级联码CMs相同类型和未缩放的场效应管。因此,在RGC的辅助放大器信号通路中,大多数现有技术中使用的与缩放场效应管相关的更高阻抗和高电容对AV的提升的阻碍较小。此外,RGC-CM与FCTA的CM使用相同的场效应管,在FCTA的直流、交流和动态响应过程和操作条件变化方面提供了更多的一致性。第三,包含最小电流选择器(MCS)和反相电流镜像放大器(ICMA)的缓冲驱动器控制非活动输出晶体管(FET)的静态电流,而互补的非反相电流镜像(CNICM)抑制由于监测FET(外部负载)电流而产生的电流浪费。输出缓冲区驱动程序本身是快速的,可以在低VDD下工作,因为它主要在当前模式下运行。蒙特卡罗(MC)和最坏情况(WC)模拟表明以下规格是可以实现的:输入电压范围轨到轨;输出电压范围从轨~ 10mV;电阻负载(RL) 5K欧姆能力;单位增益频率(fu) ~ 200KHz,相位裕度(PM) ~ 40度;电源抑制比(PSRR) ~−90dB;共模抑制比(CMRR) ~−110dB;压转率(SR) ~ 3V/ 10uS;沉降时间(ts) ~ 15uS;大小∼130嗯/。
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