Test generation for stuck-on faults in BDD-based pass-transistor logic SPL

Abstract

This paper presents a method of test generation for stuck-on faults in a pass-transistor logic SPL by logic testing. We describe how to create a discrepancy using a pre-computed table for voltage calculation. For solving a table explosion problem we present some techniques for extending the applicable scope of a restricted table in practical size. Then, we propose a simple DFT circuit. The experimental results show the effectiveness.