We have improved the optical beam induced resistance change (OBIRCH) method so as to detect (1) a current path as small as 10-50 /spl mu/A from the rear side of a chip, (2) current paths in silicide lines as narrow as 0.2 /spl mu/m. (3) high-resistivity Ti-depleted polysilicon regions in 0.2 /spl mu/m wide silicide lines, and (4) high-resistivity amorphous thin layers as thin as a few nanometers at the bottoms of vias. All detections were possible even in observation areas as wide as 5 mm/spl times/5 mm. The physical causes of these detections were characterized by focused ion beam and transmission electron microscopy.
{"title":"New capabilities of OBIRCH method for fault localization and defect detection","authors":"K. Nikawa, S. Inoue","doi":"10.1109/ATS.1997.643961","DOIUrl":"https://doi.org/10.1109/ATS.1997.643961","url":null,"abstract":"We have improved the optical beam induced resistance change (OBIRCH) method so as to detect (1) a current path as small as 10-50 /spl mu/A from the rear side of a chip, (2) current paths in silicide lines as narrow as 0.2 /spl mu/m. (3) high-resistivity Ti-depleted polysilicon regions in 0.2 /spl mu/m wide silicide lines, and (4) high-resistivity amorphous thin layers as thin as a few nanometers at the bottoms of vias. All detections were possible even in observation areas as wide as 5 mm/spl times/5 mm. The physical causes of these detections were characterized by focused ion beam and transmission electron microscopy.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124517160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fulvio Corno, P. Prinetto, M. Rebaudengo, M. Reorda, M. Violante
The constantly increasing circuit size makes the sequential ATPG problem a challenging area even when simulation-based algorithms are exploited. Several techniques have been proposed which mainly resort to logic simulation, reverting to fault simulation only when strictly required. In this paper we present a new Genetic Algorithm-based test generation method which exploits information coming from a logic simulator (e.g., the circuit activity and the reached states) to guide the search process, in particular in the fault excitation phase. Experimental results show the effectiveness of the proposed method when compared with other Genetic Algorithm-based test generators.
{"title":"Exploiting logic simulation to improve simulation-based sequential ATPG","authors":"Fulvio Corno, P. Prinetto, M. Rebaudengo, M. Reorda, M. Violante","doi":"10.1109/ATS.1997.643922","DOIUrl":"https://doi.org/10.1109/ATS.1997.643922","url":null,"abstract":"The constantly increasing circuit size makes the sequential ATPG problem a challenging area even when simulation-based algorithms are exploited. Several techniques have been proposed which mainly resort to logic simulation, reverting to fault simulation only when strictly required. In this paper we present a new Genetic Algorithm-based test generation method which exploits information coming from a logic simulator (e.g., the circuit activity and the reached states) to guide the search process, in particular in the fault excitation phase. Experimental results show the effectiveness of the proposed method when compared with other Genetic Algorithm-based test generators.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130224047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We discuss the role of power and energy in computation and test efficiency. This is done by the proposal of new computation and test efficiency models that take energy into consideration, followed by the incorporation of these models with the CMOS power consumption model to establish the following observations: (1) low power and high testability need not be competing goals in the design optimization process; (2) high power dissipation during testing may not be an issue, as long as the tester limit is not reached and the chip is not over driven; (3) high-power testing due to high speed and/or high transition activity factor is better in terms of test efficiency; and (4) for a fabricated chip with a prespecified fault coverage, testing energy is roughly constant, independent of the testing power or testing time.
{"title":"On energy efficiency of VLSI testing","authors":"Cheng-Wen Wu","doi":"10.1109/ATS.1997.643948","DOIUrl":"https://doi.org/10.1109/ATS.1997.643948","url":null,"abstract":"We discuss the role of power and energy in computation and test efficiency. This is done by the proposal of new computation and test efficiency models that take energy into consideration, followed by the incorporation of these models with the CMOS power consumption model to establish the following observations: (1) low power and high testability need not be competing goals in the design optimization process; (2) high power dissipation during testing may not be an issue, as long as the tester limit is not reached and the chip is not over driven; (3) high-power testing due to high speed and/or high transition activity factor is better in terms of test efficiency; and (4) for a fabricated chip with a prespecified fault coverage, testing energy is roughly constant, independent of the testing power or testing time.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134117102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Minimising the testing costs of boards and MCMs implies to invest in testability analysis in addition to the use of testing standards (IEEE 1149). In this paper, we propose a testability analysis method for boards and MCMs designed at Dassault Electronique. The actual prototype realised according to this new methodology aims at helping testability expert.
{"title":"Automatic testability analysis of boards and MCMs at chip level","authors":"Marc Perbost, L. Lan, C. Landrault","doi":"10.1109/ATS.1997.643913","DOIUrl":"https://doi.org/10.1109/ATS.1997.643913","url":null,"abstract":"Minimising the testing costs of boards and MCMs implies to invest in testability analysis in addition to the use of testing standards (IEEE 1149). In this paper, we propose a testability analysis method for boards and MCMs designed at Dassault Electronique. The actual prototype realised according to this new methodology aims at helping testability expert.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124443178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a concurrent fault-detection scheme for FFT processors. In the scheme, fault detection is made by comparing the pair of outputs from butterfly units based on the FFT algorithm. The hardware overhead for the scheme is O(N) where N is the number of input data. This scheme requires no extra computations for locating a pair of faulty butterfly units, therefore, the scheme can be used for highly reliable real-time systems.
{"title":"A concurrent fault-detection scheme for FFT processors","authors":"M. Tsunoyama, M. Uenoyama, T. Kabasawa","doi":"10.1109/ATS.1997.643928","DOIUrl":"https://doi.org/10.1109/ATS.1997.643928","url":null,"abstract":"This paper proposes a concurrent fault-detection scheme for FFT processors. In the scheme, fault detection is made by comparing the pair of outputs from butterfly units based on the FFT algorithm. The hardware overhead for the scheme is O(N) where N is the number of input data. This scheme requires no extra computations for locating a pair of faulty butterfly units, therefore, the scheme can be used for highly reliable real-time systems.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129629467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper shows a new family of shift register designs which enjoys a reduced latch count. Reduction in the latch count is achieved by introducing additional clocks. The reduction in latch count may reach the ultimate savings of 50%.
{"title":"On the tradeoff between number of clocks and number of latches in shift registers","authors":"J. Savir","doi":"10.1109/ATS.1997.643973","DOIUrl":"https://doi.org/10.1109/ATS.1997.643973","url":null,"abstract":"This paper shows a new family of shift register designs which enjoys a reduced latch count. Reduction in the latch count is achieved by introducing additional clocks. The reduction in latch count may reach the ultimate savings of 50%.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"6 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127404895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Hatayama, M. Ikeda, M. Takakura, Satoshi Uchiyama, Y. Sakamoto
This paper presents a design for delay testability approach to improve delay fault coverage for high speed logic LSIs. In order to simplify the model for delay test generation from two stage combinational circuit model to ordinary combinational circuit model, we add an extra latch, called sub-latch for each scannable flip-flop. A procedure for delay test generation is also developed to establish high fault coverage. The results for a practical application to logic LSIs used in mainframe computers is given to illustrate the effectiveness of our approach.
{"title":"Application of a design for delay testability approach to high speed logic LSIs","authors":"K. Hatayama, M. Ikeda, M. Takakura, Satoshi Uchiyama, Y. Sakamoto","doi":"10.1109/ATS.1997.643944","DOIUrl":"https://doi.org/10.1109/ATS.1997.643944","url":null,"abstract":"This paper presents a design for delay testability approach to improve delay fault coverage for high speed logic LSIs. In order to simplify the model for delay test generation from two stage combinational circuit model to ordinary combinational circuit model, we add an extra latch, called sub-latch for each scannable flip-flop. A procedure for delay test generation is also developed to establish high fault coverage. The results for a practical application to logic LSIs used in mainframe computers is given to illustrate the effectiveness of our approach.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129925581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the design of a low cost, test processor ASIC chip implementing multiple seed, multiple polynomial linear feedback shift register (MPMSLFSR). User programmable seed and feedback connection can be set in the pattern generator of the chip to improve fault coverage. The ASIC also supports scan-path testing. It can also be used to design external IC tester.
{"title":"A test processor chip implementing multiple seed, multiple polynomial linear feedback shift register","authors":"Z. M. Darus, I. Ahmed, L. Ali","doi":"10.1109/ATS.1997.643952","DOIUrl":"https://doi.org/10.1109/ATS.1997.643952","url":null,"abstract":"This paper presents the design of a low cost, test processor ASIC chip implementing multiple seed, multiple polynomial linear feedback shift register (MPMSLFSR). User programmable seed and feedback connection can be set in the pattern generator of the chip to improve fault coverage. The ASIC also supports scan-path testing. It can also be used to design external IC tester.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121285582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper considers two types of n-bit adders, ripple carry adders and cascaded carry look-ahead adders, with minimum tests for stuck-at-fault models. In the first part, we present two types of full adders consisting of five gates, and show their minimality. We also prove that one of the full adders can be tested by only three test patterns for single stuck-at-faults. We also present two types of 4-bit carry look-ahead adders and their minimum rests. In the second part, we consider the tests for the cascaded adders, an n-bit ripple carry adder and a 4m-bit cascaded carry look-ahead adders. These tests are considerably smaller than previously published ones.
{"title":"On the adders with minimum tests","authors":"S. Kajihara, Tsutomu Sasao","doi":"10.1109/ATS.1997.643907","DOIUrl":"https://doi.org/10.1109/ATS.1997.643907","url":null,"abstract":"This paper considers two types of n-bit adders, ripple carry adders and cascaded carry look-ahead adders, with minimum tests for stuck-at-fault models. In the first part, we present two types of full adders consisting of five gates, and show their minimality. We also prove that one of the full adders can be tested by only three test patterns for single stuck-at-faults. We also present two types of 4-bit carry look-ahead adders and their minimum rests. In the second part, we consider the tests for the cascaded adders, an n-bit ripple carry adder and a 4m-bit cascaded carry look-ahead adders. These tests are considerably smaller than previously published ones.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125223791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To make a neural network fault-tolerant, Tan et al. proposed a learning algorithm which injects intentionally the snapping of a wire one by one into a network (1992, 1992, 1993). This paper proposes a learning algorithm that injects intentionally stuck-at faults to neurons. Then by computer simulations, we investigate the recognition rate in terms of the number of snapping faults and reliabilities of lines and the learning cycle. The results show that our method is more efficient and useful than the method of Tan et al. Furthermore, we investigate the internal structure in terms of ditribution of correlations between input values of a output neuron for the respective learning methods and show that there is a significant difference of the distributions among the methods.
{"title":"On fault injection approaches for fault tolerance of feedforward neural networks","authors":"Takehiro Ito, I. Takanami","doi":"10.1109/ATS.1997.643927","DOIUrl":"https://doi.org/10.1109/ATS.1997.643927","url":null,"abstract":"To make a neural network fault-tolerant, Tan et al. proposed a learning algorithm which injects intentionally the snapping of a wire one by one into a network (1992, 1992, 1993). This paper proposes a learning algorithm that injects intentionally stuck-at faults to neurons. Then by computer simulations, we investigate the recognition rate in terms of the number of snapping faults and reliabilities of lines and the learning cycle. The results show that our method is more efficient and useful than the method of Tan et al. Furthermore, we investigate the internal structure in terms of ditribution of correlations between input values of a output neuron for the respective learning methods and show that there is a significant difference of the distributions among the methods.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133705823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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