L. Joet, A. Dezzani, F. Montaudon, F. Badets, Florent Sibille, Christian Corre, L. Chabert, R. Mina, F. Bailleuil, D. Saias, F. Paillardet, E. Perea
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引用次数: 18
Abstract
A new discrete-time receiver architecture enables to specifically circumvent CMOS integration issues, taking advantage of ZIF architectures yet escaping impact of flicker noise and second-order front-end non-linearity. This architecture, compatible with further scaling, was implemented for a GSM receiver in 90-nm CMOS. This receiver occupies 1-mm2 core area, achieves -108-dBm sensitivity, and -16-dBm IIP3. It is based on a discrete-time approach centering the baseband signal at half the sampling frequency. The receiver integrates Low-Noise Amplifier, filters and two 40-MHz sigma delta Analog to Digital Converters achieving a 12-bit resolution in 100 kHz.
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