Pub Date : 2006-12-01DOI: 10.1109/ASSCC.2006.357876
Tien-Yu Lo, C. Hung
This paper presents a high linearity operational transconductance amplifier (OTA) based on pseudo-differential structures. The linearity is improved by mobility compensation techniques as the device size is scaled down to achieve high speed operation. Transconductance tuning could be achieved by a MOS operating in the linear region. The OTA fabricated in the TSMC 0.18-mum CMOS process occupies a small area of 4.5 times 10-3 mm2. The measured third-order inter-modulation (IM3) distortion under 1-V power supply voltage remains below -52 dB up to 50 MHz for a 400 mV pp differential input. The static power consumption is 2.5 mW. Experimental results demonstrate the agreement with theoretical analyses.
提出了一种基于伪差分结构的高线性运算跨导放大器。当器件尺寸缩小以实现高速运行时，通过迁移率补偿技术改善了线性度。跨导调谐可以通过在线性区域工作的MOS来实现。采用台积电0.18 mm CMOS工艺制备的OTA占地面积很小，仅为4.5 × 10-3 mm2。对于400mv pp差分输入，在1v电源电压下，测量到的三阶互调(IM3)失真在50mhz时保持在-52 dB以下。静态功耗为2.5 mW。实验结果与理论分析一致。
{"title":"A High Speed Pseudo-Differential OTA with Mobility Compensation Technique in 1-V Power Supply Voltage","authors":"Tien-Yu Lo, C. Hung","doi":"10.1109/ASSCC.2006.357876","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357876","url":null,"abstract":"This paper presents a high linearity operational transconductance amplifier (OTA) based on pseudo-differential structures. The linearity is improved by mobility compensation techniques as the device size is scaled down to achieve high speed operation. Transconductance tuning could be achieved by a MOS operating in the linear region. The OTA fabricated in the TSMC 0.18-mum CMOS process occupies a small area of 4.5 times 10-3 mm2. The measured third-order inter-modulation (IM3) distortion under 1-V power supply voltage remains below -52 dB up to 50 MHz for a 400 mV pp differential input. The static power consumption is 2.5 mW. Experimental results demonstrate the agreement with theoretical analyses.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128985137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/ASSCC.2006.357899
Jongsik Kim, Tae Wook Kim, M. Jeong, Boeun Kim, Hyunchol Shin
A CMOS driver amplifier employs two design techniques to improve its linearity in wide output power level. First, multiple-gated transistor (MGTR) technique with two auxiliary transistors extends the linear region further compared with MGTR with single auxiliary transistor. Second, resistive source degeneration significantly suppresses the unwanted 2nd-harmonic feedback effect caused by an inductive source degeneration. A 2.4-GHz differential driver amplifier has been implemented in 0.18 mum CMOS for Mobile WiMAX and Korean WiBro applications. It shows that the linear region with OIP3 of >+20dBm is extended up to an output power of -5 dBm, while achieving a maximum OIP3 of +28 dBm, OPldB of +7.8 dBm, and a power gain of 9.2 dB with dc power consumption of 1.8V and 18.7 mA.
{"title":"A 2.4-GHz CMOS Driver Amplifier Based on Multiple-Gated Transistor and Resistive Source Degeneration for Mobile WiMAX","authors":"Jongsik Kim, Tae Wook Kim, M. Jeong, Boeun Kim, Hyunchol Shin","doi":"10.1109/ASSCC.2006.357899","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357899","url":null,"abstract":"A CMOS driver amplifier employs two design techniques to improve its linearity in wide output power level. First, multiple-gated transistor (MGTR) technique with two auxiliary transistors extends the linear region further compared with MGTR with single auxiliary transistor. Second, resistive source degeneration significantly suppresses the unwanted 2nd-harmonic feedback effect caused by an inductive source degeneration. A 2.4-GHz differential driver amplifier has been implemented in 0.18 mum CMOS for Mobile WiMAX and Korean WiBro applications. It shows that the linear region with OIP3 of >+20dBm is extended up to an output power of -5 dBm, while achieving a maximum OIP3 of +28 dBm, OPldB of +7.8 dBm, and a power gain of 9.2 dB with dc power consumption of 1.8V and 18.7 mA.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124098524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/ASSCC.2006.357856
C. Tang, Cheng-Chi Wong, Chih-Lung Chen, Chien-Ching Lin, Hsie-Chia Chang
In this paper, a high-speed Max-Log MAP decoder is presented for soft-in and soft-out trellis decoding. The high throughput is achieved with a two-dimensional ACS design on the high-radix trellis structure, resulting in a highly parallel and area-efficient decoder. We further apply the retiming technique to reduce the critical path delay of ACS operation. After 0.13 mum CMOS chip implementation, the decoder occupies 1.96 mm2 area containing 220 K gates. The estimated timing under the 1.08 V supply and the worst case corner shows that the test chip can achieve the maximum 952 MS/s throughput. To our knowledge, the present Max-Log MAP decoder has the highest throughput with the modest hardware cost.
本文提出了一种用于软入和软出栅格译码的高速最大对数MAP解码器。高吞吐量是通过在高基数网格结构上的二维ACS设计实现的，从而产生高度并行和面积高效的解码器。我们进一步应用重定时技术来降低ACS操作的关键路径延迟。在0.13 mm CMOS芯片实现后，解码器占地1.96 mm2，包含220 K门。在1.08 V电源和最坏情况下的估计时序表明，测试芯片可以达到最大952 MS/s的吞吐量。据我们所知，目前的最大日志MAP解码器具有最高的吞吐量和适度的硬件成本。
{"title":"A 952MS/s Max-Log MAP Decoder Chip using Radix-4 × 4 ACS Architecture","authors":"C. Tang, Cheng-Chi Wong, Chih-Lung Chen, Chien-Ching Lin, Hsie-Chia Chang","doi":"10.1109/ASSCC.2006.357856","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357856","url":null,"abstract":"In this paper, a high-speed Max-Log MAP decoder is presented for soft-in and soft-out trellis decoding. The high throughput is achieved with a two-dimensional ACS design on the high-radix trellis structure, resulting in a highly parallel and area-efficient decoder. We further apply the retiming technique to reduce the critical path delay of ACS operation. After 0.13 mum CMOS chip implementation, the decoder occupies 1.96 mm2 area containing 220 K gates. The estimated timing under the 1.08 V supply and the worst case corner shows that the test chip can achieve the maximum 952 MS/s throughput. To our knowledge, the present Max-Log MAP decoder has the highest throughput with the modest hardware cost.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129985771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/ASSCC.2006.357862
S. Hiratsuka, S. Goto, T. Ikenaga
Motion estimation (ME) is a key processing in video encoding systems. Since it requires huge computational complexity, many algorithms and LSI architectures have been proposed to reduce it. Conventional LSIs, however, are not sufficient for mobile applications which require both flexibility and low power dissipation. This paper describes an application specific instruction processor (ASIP) LSI for ME processing. It has a dedicated unit for SAD (sum of absolute difference) operations. By applying our proposed ultra-low ME algorithm named ULCMEA, it can reduce power while keeping high flexibility. A chip capable of operating at 80 MHz was fabricated using TSMC 0.18-mum CMOS technology. 15 K logic gates and 32 Kbit SRAM have been integrated into 1.4 mm chip. Typical power dissipation is 0.3-mW for QCIF 15 frame/ sec ME processing.
运动估计是视频编码系统中的一个关键处理环节。由于它需要巨大的计算复杂度，已经提出了许多算法和LSI架构来降低它。然而，传统的lsi对于需要灵活性和低功耗的移动应用来说是不够的。本文介绍了一种用于ME处理的专用指令处理器(ASIP) LSI。它有一个用于绝对差和操作的专用单元。采用我们提出的超低ME算法ULCMEA，可以在降低功耗的同时保持较高的灵活性。采用台积电0.18 μ m CMOS技术制备了工作频率为80 MHz的芯片。1.4 mm芯片集成了15k逻辑门和32kbit SRAM。对于QCIF 15帧/秒的ME处理，典型功耗为0.3 mw。
{"title":"A 0.3mW 1.4mm2 Motion Estimation Processor for Mobile Video Application","authors":"S. Hiratsuka, S. Goto, T. Ikenaga","doi":"10.1109/ASSCC.2006.357862","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357862","url":null,"abstract":"Motion estimation (ME) is a key processing in video encoding systems. Since it requires huge computational complexity, many algorithms and LSI architectures have been proposed to reduce it. Conventional LSIs, however, are not sufficient for mobile applications which require both flexibility and low power dissipation. This paper describes an application specific instruction processor (ASIP) LSI for ME processing. It has a dedicated unit for SAD (sum of absolute difference) operations. By applying our proposed ultra-low ME algorithm named ULCMEA, it can reduce power while keeping high flexibility. A chip capable of operating at 80 MHz was fabricated using TSMC 0.18-mum CMOS technology. 15 K logic gates and 32 Kbit SRAM have been integrated into 1.4 mm chip. Typical power dissipation is 0.3-mW for QCIF 15 frame/ sec ME processing.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134541127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/ASSCC.2006.357936
Wei-Zen Chen, Chin-Yuan Wei, Jennie Chen
This paper describes the design of a 0.625-3.125 Gbps, burst mode clock and data recovery circuit in a 0.18 mum CMOS process. A novel bang-bang PD incorporating binary-search phase acquisition and dynamic loop filter is proposed to achieve rapid phase locking. The measured locking time is less than 1 ns (@ 3.125 Gbps). Integrating with a limiting amplifier and a 1 to 4 demultiplexer on a single chip, the total power dissipation is 78 mW. The input sensitivity of the burst mode receiver is about 30 mV for BER less than 10-10.
{"title":"A Wide-Range Burst Mode Clock and Data Recovery Circuit","authors":"Wei-Zen Chen, Chin-Yuan Wei, Jennie Chen","doi":"10.1109/ASSCC.2006.357936","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357936","url":null,"abstract":"This paper describes the design of a 0.625-3.125 Gbps, burst mode clock and data recovery circuit in a 0.18 mum CMOS process. A novel bang-bang PD incorporating binary-search phase acquisition and dynamic loop filter is proposed to achieve rapid phase locking. The measured locking time is less than 1 ns (@ 3.125 Gbps). Integrating with a limiting amplifier and a 1 to 4 demultiplexer on a single chip, the total power dissipation is 78 mW. The input sensitivity of the burst mode receiver is about 30 mV for BER less than 10-10.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122215460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/ASSCC.2006.357852
C. Su, Po-Chen Lin, Hungwen Lu
This paper presented an inverter based 3rd order sigma-delta ADC. Cascode structure and auto-zeroing mechanism are proposed for the gain enhancement and offset cancellation. The ADC has been implemented in TSMC 2P6M 0.18 μm CMOS technology with a core area of 0.54 mm2. The measurement results show that for the 1-V supply, 20-KHz bandwidth, and 2-MHz sampling rate, the power consumption is 42 μW and the dynamic range of 66.02 dB.
{"title":"An Inverter Based 2-MHz 42-μW ΔΣ ADC with 20-KHz Bandwidth and 66dB Dynamic Range","authors":"C. Su, Po-Chen Lin, Hungwen Lu","doi":"10.1109/ASSCC.2006.357852","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357852","url":null,"abstract":"This paper presented an inverter based 3rd order sigma-delta ADC. Cascode structure and auto-zeroing mechanism are proposed for the gain enhancement and offset cancellation. The ADC has been implemented in TSMC 2P6M 0.18 μm CMOS technology with a core area of 0.54 mm2. The measurement results show that for the 1-V supply, 20-KHz bandwidth, and 2-MHz sampling rate, the power consumption is 42 μW and the dynamic range of 66.02 dB.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127668804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/ASSCC.2006.357907
M. Ker, Chang-Tzu Wang
A new electrostatic discharge (ESD) protection design by using only 1timesVDD low-voltage devices for mixed-voltage I/O buffer with 3timesVDD input tolerance is proposed. A special ESD detection circuit has been proposed to improve ESD protection efficiency of ESD clamp device by substrate-triggered technique to achieve high ESD level. This design has been successfully verified in a 0.13-mum CMOS process to provide an excellent circuit solution for on-chip ESD protection in the mixed-voltage I/O buffers with 3timesVDD input tolerance.
提出了一种仅使用1倍vdd低压器件用于输入容限为3倍vdd的混合电压I/O缓冲器的新型静电放电保护设计。提出了一种特殊的ESD检测电路，通过衬底触发技术提高ESD钳位器件的ESD保护效率，达到较高的ESD水平。该设计已在0.13 μ m CMOS工艺中成功验证，为具有3倍vdd输入容限的混合电压I/O缓冲器中的片上ESD保护提供了出色的电路解决方案。
{"title":"ESD Protection Design by Using Only 1×VDD Low-Voltage Devices for Mixed-Voltage I/O Buffers with 3×VDD Input Tolerance","authors":"M. Ker, Chang-Tzu Wang","doi":"10.1109/ASSCC.2006.357907","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357907","url":null,"abstract":"A new electrostatic discharge (ESD) protection design by using only 1timesVDD low-voltage devices for mixed-voltage I/O buffer with 3timesVDD input tolerance is proposed. A special ESD detection circuit has been proposed to improve ESD protection efficiency of ESD clamp device by substrate-triggered technique to achieve high ESD level. This design has been successfully verified in a 0.13-mum CMOS process to provide an excellent circuit solution for on-chip ESD protection in the mixed-voltage I/O buffers with 3timesVDD input tolerance.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115489011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/ASSCC.2006.357943
Chih-Jen Cheng, Shuenn-Yuh Lee, Yuan Lo
An ultra-low voltage adaptive Sigma-Delta Analog-to-Digital Converter (SDADC) with a 10-bit dynamic range for bio-microsystem applications is presented. The proposed SDADC includes a Switched-current Sigma-Delta Modulator (SISDM) and a digital decimator. Moreover, a new single-multiplier structure is presented to implement the Finite Impulse Response (FIR) digital filters which are the major hardware elements in the decimator. Measurement results show that the SISDM has a dynamic range over 6 dB and a power consumption of 180 muW with an input signal of 1.25 kHz sinusoid wave and 5 kHz bandwidth under a single 0.8 V power supply for ENG signals. Besides, the post layout simulations of SDADC including SISDM and decimator reveal that the dynamic range is still over 60 dB without harming by digital circuits.
{"title":"A Low-Voltage and Area-Efficient Adaptive SI SDADC for Bio-Acquisition Microsystems","authors":"Chih-Jen Cheng, Shuenn-Yuh Lee, Yuan Lo","doi":"10.1109/ASSCC.2006.357943","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357943","url":null,"abstract":"An ultra-low voltage adaptive Sigma-Delta Analog-to-Digital Converter (SDADC) with a 10-bit dynamic range for bio-microsystem applications is presented. The proposed SDADC includes a Switched-current Sigma-Delta Modulator (SISDM) and a digital decimator. Moreover, a new single-multiplier structure is presented to implement the Finite Impulse Response (FIR) digital filters which are the major hardware elements in the decimator. Measurement results show that the SISDM has a dynamic range over 6 dB and a power consumption of 180 muW with an input signal of 1.25 kHz sinusoid wave and 5 kHz bandwidth under a single 0.8 V power supply for ENG signals. Besides, the post layout simulations of SDADC including SISDM and decimator reveal that the dynamic range is still over 60 dB without harming by digital circuits.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126859459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/ASSCC.2006.357942
Hio Leong Chao, D. Ma, M. Koen, P. Prazak
A CMOS current feedback amplifier (CFA) for ultrasound diagnostic applications is proposed. Unlike traditional CFAs, this design employs a new symmetrical and compact architecture, without the use of common-mode feedback (CMFB) circuitry. The design proposes an active feedback technique to drastically enhance the gain-bandwidth independence. It is also the first CFA to adopt Miller compensation for better frequency response with smaller compensation capacitor. The proposed CFA was fabricated and tested with a standard 0.35 mum CMOS process with competitive performance to its Bipolar and BiCMOS counterparts. The active die area is 0.052 mm2. Experiment results show that the CFA exhibits a minimum bandwidth of 4.5 MHz with a variable gain range of 0 to 46 dB, and a power dissipation of 2.18 mW.
提出了一种用于超声诊断的CMOS电流反馈放大器。与传统的cfa不同，该设计采用了一种新的对称和紧凑的架构，没有使用共模反馈(CMFB)电路。该设计提出了一种主动反馈技术，以大大提高增益-带宽独立性。它也是第一个采用米勒补偿的CFA，以更小的补偿电容获得更好的频率响应。所提出的CFA是用标准的0.35 μ m CMOS工艺制造和测试的，具有与双极和BiCMOS同行竞争的性能。活动模面积为0.052 mm2。实验结果表明，该滤波器的最小带宽为4.5 MHz，增益范围为0 ~ 46 dB，功耗为2.18 mW。
{"title":"CMOS Low-Power Variable-Gain CMFB-Free Current Feedback Amplifier for Ultrasound Diagnostic Applications","authors":"Hio Leong Chao, D. Ma, M. Koen, P. Prazak","doi":"10.1109/ASSCC.2006.357942","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357942","url":null,"abstract":"A CMOS current feedback amplifier (CFA) for ultrasound diagnostic applications is proposed. Unlike traditional CFAs, this design employs a new symmetrical and compact architecture, without the use of common-mode feedback (CMFB) circuitry. The design proposes an active feedback technique to drastically enhance the gain-bandwidth independence. It is also the first CFA to adopt Miller compensation for better frequency response with smaller compensation capacitor. The proposed CFA was fabricated and tested with a standard 0.35 mum CMOS process with competitive performance to its Bipolar and BiCMOS counterparts. The active die area is 0.052 mm2. Experiment results show that the CFA exhibits a minimum bandwidth of 4.5 MHz with a variable gain range of 0 to 46 dB, and a power dissipation of 2.18 mW.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128388525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/ASSCC.2006.357923
Ying-Zu Lin, Yen-Ting Liu, Soon-Jyh Chang
A 6-bit flash ADC is fabricated in TSMC CMOS 0.18-μm 1P6M process and supports a sampling rate up to 2 GS/s. The proposed ADC consists of a track-and-hold amplifier, a comparator array, a four-channel ROM-based 64-to-6 encoder, a multiplexer, and a clock generation and distribution system. Instead of traditional latch-based comparators used in high-speed ADCs, continuous-time comparators are employed to minimize kick-back noises and offsets. When the sampling frequency is 2 GHz, the measured SNDR is 30.01 dB at input frequency around 200 MHz. The ADC consumes 255 mW from a 1.8-V supply and occupies 1.88 x 1.92 mm2 of die area. In addition to chip implementation, an analysis on resistive averaging network in frequency domain is presented. Characteristics of averaged differential pairs related to input frequency are revealed.
{"title":"A 6-Bit 2-GS/s Flash Aanlog-to-Digital Converter in 0.18-μm CMOS Process","authors":"Ying-Zu Lin, Yen-Ting Liu, Soon-Jyh Chang","doi":"10.1109/ASSCC.2006.357923","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357923","url":null,"abstract":"A 6-bit flash ADC is fabricated in TSMC CMOS 0.18-μm 1P6M process and supports a sampling rate up to 2 GS/s. The proposed ADC consists of a track-and-hold amplifier, a comparator array, a four-channel ROM-based 64-to-6 encoder, a multiplexer, and a clock generation and distribution system. Instead of traditional latch-based comparators used in high-speed ADCs, continuous-time comparators are employed to minimize kick-back noises and offsets. When the sampling frequency is 2 GHz, the measured SNDR is 30.01 dB at input frequency around 200 MHz. The ADC consumes 255 mW from a 1.8-V supply and occupies 1.88 x 1.92 mm2 of die area. In addition to chip implementation, an analysis on resistive averaging network in frequency domain is presented. Characteristics of averaged differential pairs related to input frequency are revealed.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127583168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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