{"title":"A SHA-3 Co-Processor for IoT Applications","authors":"Igor L.R. Azevedo, A. S. Nery, A. Sena","doi":"10.1109/WCNPS50723.2020.9263759","DOIUrl":null,"url":null,"abstract":"The Secure Hash Algorithm 3 (SHA-3) is the latest member of the secure hash family of algorithms (SHA) on top of which several technologies are built upon, such as in Blockchain, security applications and protocols, including TLS, SSL, PGP, SSH, IPsec, and S/MIME. Due to tighter processing and power efficiency constraints often present in embedded applications, hardware architectures such as FPGAs (Field-Programmable Gate Array) can be employed to enable the design and implementation of efficient hardware accelerators. Thus, this work implements a SHA-3 Co-Processor in FPGA suitable for IoT applications. Performance, Circuit-area and Energy consumption results show that the Co-Processor is about 65% faster than the ARM Cortex-A9 processor that is also equipped in the FPGA chip, as well as in many IoT embedded systems.","PeriodicalId":385668,"journal":{"name":"2020 Workshop on Communication Networks and Power Systems (WCNPS)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 Workshop on Communication Networks and Power Systems (WCNPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WCNPS50723.2020.9263759","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The Secure Hash Algorithm 3 (SHA-3) is the latest member of the secure hash family of algorithms (SHA) on top of which several technologies are built upon, such as in Blockchain, security applications and protocols, including TLS, SSL, PGP, SSH, IPsec, and S/MIME. Due to tighter processing and power efficiency constraints often present in embedded applications, hardware architectures such as FPGAs (Field-Programmable Gate Array) can be employed to enable the design and implementation of efficient hardware accelerators. Thus, this work implements a SHA-3 Co-Processor in FPGA suitable for IoT applications. Performance, Circuit-area and Energy consumption results show that the Co-Processor is about 65% faster than the ARM Cortex-A9 processor that is also equipped in the FPGA chip, as well as in many IoT embedded systems.