A SHA-3 Co-Processor for IoT Applications

Igor L.R. Azevedo, A. S. Nery, A. Sena
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Abstract

The Secure Hash Algorithm 3 (SHA-3) is the latest member of the secure hash family of algorithms (SHA) on top of which several technologies are built upon, such as in Blockchain, security applications and protocols, including TLS, SSL, PGP, SSH, IPsec, and S/MIME. Due to tighter processing and power efficiency constraints often present in embedded applications, hardware architectures such as FPGAs (Field-Programmable Gate Array) can be employed to enable the design and implementation of efficient hardware accelerators. Thus, this work implements a SHA-3 Co-Processor in FPGA suitable for IoT applications. Performance, Circuit-area and Energy consumption results show that the Co-Processor is about 65% faster than the ARM Cortex-A9 processor that is also equipped in the FPGA chip, as well as in many IoT embedded systems.
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面向物联网应用的SHA-3协处理器
安全哈希算法3 (SHA-3)是安全哈希算法家族(SHA)的最新成员,在此基础上构建了许多技术,例如b区块链、安全应用程序和协议,包括TLS、SSL、PGP、SSH、IPsec和S/MIME。由于嵌入式应用中经常出现更严格的处理和功率效率限制,可以采用fpga(现场可编程门阵列)等硬件架构来实现高效硬件加速器的设计和实现。因此,本工作在FPGA中实现了适合物联网应用的SHA-3协处理器。性能、电路面积和能耗结果表明,协处理器比ARM Cortex-A9处理器快约65%,ARM Cortex-A9处理器也配备在FPGA芯片中,以及许多物联网嵌入式系统中。
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