The “buffering” role of high-к in post breakdown degradation immunity of advanced dual layer dielectric gate stacks

Abstract

Post breakdown (BD) reliability is an important area of study in ultra-thin gate dielectrics as it has significant implications on the performance degradation, lifetime, reliability margin and power dissipation of advanced sub-22 nm transistors and circuits. A prolonged phase of post-BD can ensure we can live with the circuit with moderate performance and error-free operation, even if the soft breakdown (SBD) events occur early. While analysis of post-BD is simple and straightforward for single layer SiO2/SiON stacks, the number of possible scenarios of post-BD increases when analyzing high-κ-interfacial layer (HK-IL) based technology. This is because the sequence of BD (whether HK or IL fails first followed by the other one) and the competition between multiple SBD in one of these layers, dilative wear-out of a single SBD spot and the possibility of a successive localized BD above/below the HK/IL BD percolation spot (with or without metal filamentation) are all possible phenomena that can be classified as post-BD. The likelihood of occurrence of these various possibilities will determine the immunity of the stack to post-BD degradation. We will investigate each of these scenarios in detail in this work in order to provide a comprehensive assessment of post-BD reliability of state-of-the-art technology. Our analysis on a HK:IL = 25:12Å stack supported by electrical, physical and modeling results provides clear evidence that circuit failure at operating conditions can only be due to multiple SBD events within the IL layer and that the HK is very robust and resilient to breakdown.