Pub Date : 2013-06-18DOI: 10.1109/IRPS.2013.6531973
M. Katoozi, E. Cannon, T. Dao, K. Aitken, S. Fischer, T. Amort, R. Brees, J. Tostenrude
A general method for creating an age-aware library of cells, including the impact of multiple reliability degradation mechanisms, is presented. The underlying degradation models take into account key reliability-impacting parameters such as input slew rate, output load, signal toggle rate, signal activity factor, output buffer size and age. A framework for using this age-aware library to analyze the aging of digital Integrated Circuit (IC) timing performance using existing Electronic Design Automation (EDA) methodologies is also discussed.
{"title":"An age-aware library for reliability simulation of digital ICs","authors":"M. Katoozi, E. Cannon, T. Dao, K. Aitken, S. Fischer, T. Amort, R. Brees, J. Tostenrude","doi":"10.1109/IRPS.2013.6531973","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531973","url":null,"abstract":"A general method for creating an age-aware library of cells, including the impact of multiple reliability degradation mechanisms, is presented. The underlying degradation models take into account key reliability-impacting parameters such as input slew rate, output load, signal toggle rate, signal activity factor, output buffer size and age. A framework for using this age-aware library to analyze the aging of digital Integrated Circuit (IC) timing performance using existing Electronic Design Automation (EDA) methodologies is also discussed.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127773197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-18DOI: 10.1109/IRPS.2013.6532071
C. Yeh, M. Ker
A resistor-less power-rail ESD clamp circuit realized with only thin gate oxide devices, and with SCR as main ESD clamp device, has been proposed and verified in a 65nm 1V CMOS process. Skillfully utilizing the gate leakage currents to realize the equivalent resistors in the ESD-transient detection circuit, the RC-based ESD-transient detection mechanism can be achieved without using an actual resistor to reduce the layout area in I/O cells. From the measured results, the proposed power-rail ESD clamp circuit with SCR width of 45μm can achieve 5kV HBM and 400V MM ESD levels under the ESD stress event, while consuming only a standby leakage current of 1.43nA at 25°C under the normal circuit operating condition with 1V bias.
{"title":"Resistor-less power-rail ESD clamp circuit with ultra-low leakage current in 65nm CMOS process","authors":"C. Yeh, M. Ker","doi":"10.1109/IRPS.2013.6532071","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532071","url":null,"abstract":"A resistor-less power-rail ESD clamp circuit realized with only thin gate oxide devices, and with SCR as main ESD clamp device, has been proposed and verified in a 65nm 1V CMOS process. Skillfully utilizing the gate leakage currents to realize the equivalent resistors in the ESD-transient detection circuit, the RC-based ESD-transient detection mechanism can be achieved without using an actual resistor to reduce the layout area in I/O cells. From the measured results, the proposed power-rail ESD clamp circuit with SCR width of 45μm can achieve 5kV HBM and 400V MM ESD levels under the ESD stress event, while consuming only a standby leakage current of 1.43nA at 25°C under the normal circuit operating condition with 1V bias.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116767967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532076
D. Wang, A. Zhao, L. Yu, J. Wu, V. Chang, W. Chien
The effect of early failure model on upstream EM reliability and its improvements are investigated in a 45nm CMOS process. The effective process optimizations of tapered via profile by organic under layer (ODL) over etch (OE) at chamfer area and enlarged trench CD have been analyzed and discussed. Recent observations shown tapered via profile at chamfer area can get much larger angle for barrier seed deposition and the trench CD enlargement can get larger deposition angle and larger process window for photo alignment process at the vertical section. With a better step coverage, the defect-free barrier seed layer will suppress via void formation and improve the upstream EM reliability.
{"title":"Early failure model analysis and improvement of the upstream electromigration in 45nm Cu low-k interconnects","authors":"D. Wang, A. Zhao, L. Yu, J. Wu, V. Chang, W. Chien","doi":"10.1109/IRPS.2013.6532076","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532076","url":null,"abstract":"The effect of early failure model on upstream EM reliability and its improvements are investigated in a 45nm CMOS process. The effective process optimizations of tapered via profile by organic under layer (ODL) over etch (OE) at chamfer area and enlarged trench CD have been analyzed and discussed. Recent observations shown tapered via profile at chamfer area can get much larger angle for barrier seed deposition and the trench CD enlargement can get larger deposition angle and larger process window for photo alignment process at the vertical section. With a better step coverage, the defect-free barrier seed layer will suppress via void formation and improve the upstream EM reliability.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115409251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532099
S. Souiki, Q. Hubert, G. Navarro, A. Persico, C. Jahan, E. Henaff, V. Delaye, D. Blachier, V. Sousa, L. Perniola, E. Vianello, B. De Salvo
In this paper, we investigate the performances of carbon-doped Ge2Sb2Te5 films (named hereafter GST) which have been integrated together with a thin titanium capping layer into Phase-Change Memory devices. We show that the carbon content into GST and the titanium cap layer thickness can be optimized to obtain an Amorphous As-Deposited (A-AD) phase which is stable under both the typical Back End-Of-Line (BEOL) thermal budget (2 min at 400°C) and standard Pb-free soldering reflow process conditions (temperature peak at 260°C). Therefore, the material obtained at fab-out keeps its disordered phase and can be used to precode one state of information stable against the standard soldering reflow (peak at 260°C). We propose to use this high resistance state together with an electrically induced low resistance state to pre-code the memory prior to PCB manufacturing.
{"title":"Reliability study of carbon-doped GST stack robust against Pb-free soldering reflow","authors":"S. Souiki, Q. Hubert, G. Navarro, A. Persico, C. Jahan, E. Henaff, V. Delaye, D. Blachier, V. Sousa, L. Perniola, E. Vianello, B. De Salvo","doi":"10.1109/IRPS.2013.6532099","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532099","url":null,"abstract":"In this paper, we investigate the performances of carbon-doped Ge2Sb2Te5 films (named hereafter GST) which have been integrated together with a thin titanium capping layer into Phase-Change Memory devices. We show that the carbon content into GST and the titanium cap layer thickness can be optimized to obtain an Amorphous As-Deposited (A-AD) phase which is stable under both the typical Back End-Of-Line (BEOL) thermal budget (2 min at 400°C) and standard Pb-free soldering reflow process conditions (temperature peak at 260°C). Therefore, the material obtained at fab-out keeps its disordered phase and can be used to precode one state of information stable against the standard soldering reflow (peak at 260°C). We propose to use this high resistance state together with an electrically induced low resistance state to pre-code the memory prior to PCB manufacturing.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121831757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532061
C. Van Dam, M. Hauser
Accurate CMOS reliability simulations are required at the circuit design stage in order to predict product lifetime. The physical mechanisms that cause transistor performance to degrade depend on operating conditions (temperature, bias), scale and technology of their design, as well as how the devices are topologically interconnected, loaded, and switched. This study investigates reliability model to hardware correlation of Cu 45nm Silicon-On-Insulator (SOI) ring oscillators, variations of which are altogether typical of digital logic paths. The contributions from physical degradation mechanisms of Negative Bias Temperature Instability (NBTI) and Hot-Carrier Injection (HCI) were modeled in RelXpert to produce degraded Spectre netlists. Simulations were found to be within acceptable accuracy for estimating aging induced performance changes in hardware, quantitatively compared in terms of the %-difference in the time-slope of the power regression of frequency degradation, as well as in the actual %-frequency degradation as a function of time. The main contribution of this work is in the accurate prediction of the extent of the dominant component degradation mechanisms in what may be the smallest scale thin-oxide devices that will ever be fabricated in production, reflecting that the NBTI and HCI mechanisms are well understood across scale variation approaching the atomic limit.
{"title":"Ring oscillator reliability model to hardware correlation in 45nm SOI","authors":"C. Van Dam, M. Hauser","doi":"10.1109/IRPS.2013.6532061","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532061","url":null,"abstract":"Accurate CMOS reliability simulations are required at the circuit design stage in order to predict product lifetime. The physical mechanisms that cause transistor performance to degrade depend on operating conditions (temperature, bias), scale and technology of their design, as well as how the devices are topologically interconnected, loaded, and switched. This study investigates reliability model to hardware correlation of Cu 45nm Silicon-On-Insulator (SOI) ring oscillators, variations of which are altogether typical of digital logic paths. The contributions from physical degradation mechanisms of Negative Bias Temperature Instability (NBTI) and Hot-Carrier Injection (HCI) were modeled in RelXpert to produce degraded Spectre netlists. Simulations were found to be within acceptable accuracy for estimating aging induced performance changes in hardware, quantitatively compared in terms of the %-difference in the time-slope of the power regression of frequency degradation, as well as in the actual %-frequency degradation as a function of time. The main contribution of this work is in the accurate prediction of the extent of the dominant component degradation mechanisms in what may be the smallest scale thin-oxide devices that will ever be fabricated in production, reflecting that the NBTI and HCI mechanisms are well understood across scale variation approaching the atomic limit.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117245107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532001
T. Parrassin, V. Huard, X. Federspiel, E. Pion, D. Ney, P. Larre, D. Croain, A. Mishra, R. Chevallier, A. Bravaix
This paper introduces for the first time a new test structure for electromigration which allows increased statistics and reliability tests in a testchip under typical High Temperature Operating Life experimental ranges. Following the electrical analysis, a large panel of failure analysis methodologies was suitably used to categorize defects such as size, location, resistance impact, etc. This thorough analysis allows us to confirm that silicon failures are accurately predicted by our electromigration checker, based on reliability design rules.
{"title":"Statistical electrical and failure analysis of electromigration in advanced CMOS nodes for accurate design rules checker","authors":"T. Parrassin, V. Huard, X. Federspiel, E. Pion, D. Ney, P. Larre, D. Croain, A. Mishra, R. Chevallier, A. Bravaix","doi":"10.1109/IRPS.2013.6532001","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532001","url":null,"abstract":"This paper introduces for the first time a new test structure for electromigration which allows increased statistics and reliability tests in a testchip under typical High Temperature Operating Life experimental ranges. Following the electrical analysis, a large panel of failure analysis methodologies was suitably used to categorize defects such as size, location, resistance impact, etc. This thorough analysis allows us to confirm that silicon failures are accurately predicted by our electromigration checker, based on reliability design rules.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121041643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532021
E. Wu
Unlike previously accepted notions, we present the experimental evidence that the first BD events (TBD) follows a single-Weibull distribution (2-parameters) for high-κ/SiO2 stack dielectrics using large-sample size experiments and fast-time measurements. It is found that neglecting the initial failure mode can lead to a false bending at low percentiles. In contrast, a bimodality with strong bending in residual time (TRES=TFAIL-TBD) distributions is commonly observed in all cases, suggesting a universal bimodal progressive BD (PBD) distribution which plays a fundamental role in circuit reliability. Using a general Monte Carlo simulator including the multiple-spot competing PBD mode with a 5-parameter model [1] for PBD distribution, we have obtained an excellent agreement by simultaneously fitting three distributions: TBD, TRES, and TFAIL(IFAIL), thus resolving a wide range of conflicting observations in recent publications in a coherent framework.
{"title":"A new formulation of breakdown model for high-к/SiO2 stack dielectrics","authors":"E. Wu","doi":"10.1109/IRPS.2013.6532021","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532021","url":null,"abstract":"Unlike previously accepted notions, we present the experimental evidence that the first BD events (TBD) follows a single-Weibull distribution (2-parameters) for high-κ/SiO2 stack dielectrics using large-sample size experiments and fast-time measurements. It is found that neglecting the initial failure mode can lead to a false bending at low percentiles. In contrast, a bimodality with strong bending in residual time (TRES=TFAIL-TBD) distributions is commonly observed in all cases, suggesting a universal bimodal progressive BD (PBD) distribution which plays a fundamental role in circuit reliability. Using a general Monte Carlo simulator including the multiple-spot competing PBD mode with a 5-parameter model [1] for PBD distribution, we have obtained an excellent agreement by simultaneously fitting three distributions: TBD, TRES, and TFAIL(IFAIL), thus resolving a wide range of conflicting observations in recent publications in a coherent framework.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116463635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531942
Soo Youn Kim, G. Panagopoulos, Chih-Hsiang Ho, M. Katoozi, E. Cannon, K. Roy
We developed a compact SPICE model capable of modeling the increases in post-breakdown (BD) gate current (IG_BD) due to time-dependent dielectric breakdown (TDDB), for circuit level simulations. IG_BD is determined by the random shape of the BD path given by the percolation model and the location of BD path. The statistical nature of our analysis provides different IG_BD for each transistor and hence, can be efficient for statistical circuit simulation. The generated gate current is fed into the proposed SPICE model incorporating transistor threshold voltage shift (VTH-SHIFT) due to bias temperature instability (BTI). We present simulation results of a ring oscillator using our model and compare the results to experimental data from an ultrathin CMOS technology. We also show that IDDQ is a more representative signature of TDDB degradation than the delay of a ring oscillator.
{"title":"A compact SPICE model for statistical post-breakdown gate current increase due to TDDB","authors":"Soo Youn Kim, G. Panagopoulos, Chih-Hsiang Ho, M. Katoozi, E. Cannon, K. Roy","doi":"10.1109/IRPS.2013.6531942","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531942","url":null,"abstract":"We developed a compact SPICE model capable of modeling the increases in post-breakdown (BD) gate current (IG_BD) due to time-dependent dielectric breakdown (TDDB), for circuit level simulations. IG_BD is determined by the random shape of the BD path given by the percolation model and the location of BD path. The statistical nature of our analysis provides different IG_BD for each transistor and hence, can be efficient for statistical circuit simulation. The generated gate current is fed into the proposed SPICE model incorporating transistor threshold voltage shift (VTH-SHIFT) due to bias temperature instability (BTI). We present simulation results of a ring oscillator using our model and compare the results to experimental data from an ultrathin CMOS technology. We also show that IDDQ is a more representative signature of TDDB degradation than the delay of a ring oscillator.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114400989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532066
A. Singulani, H. Ceric, E. Langer, S. Carniello
Through Silicon Via (TSV) is a lead topic in interconnects and 3D integration research, mainly due to numerous anticipated advantages. However, several challenges must still be overcome if large scale production is to be achieved. In this work, we have studied effects of Bosch scallops concerning mechanical reliability for a specific TSV technology. The presence of scallops on the TSV wall modifies the stress distribution along the via. By means of Finite Element Method (FEM) simulations, we could assess this change and understand the process. The achieved results support experiments and give a better insight into the influence of scallops on the stress in an open TSV.
{"title":"Effects of Bosch scallops on metal layer stress of an open Through Silicon Via technology","authors":"A. Singulani, H. Ceric, E. Langer, S. Carniello","doi":"10.1109/IRPS.2013.6532066","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532066","url":null,"abstract":"Through Silicon Via (TSV) is a lead topic in interconnects and 3D integration research, mainly due to numerous anticipated advantages. However, several challenges must still be overcome if large scale production is to be achieved. In this work, we have studied effects of Bosch scallops concerning mechanical reliability for a specific TSV technology. The presence of scallops on the TSV wall modifies the stress distribution along the via. By means of Finite Element Method (FEM) simulations, we could assess this change and understand the process. The achieved results support experiments and give a better insight into the influence of scallops on the stress in an open TSV.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128501593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531958
J. Franco, B. Kaczer, M. Toledano-Luque, P. Roussel, G. Groeseneken, B. Schwarz, M. Bina, M. Waltl, P. Wagner, T. Grasser
We study the impact of individual charged gate oxide defects on the characteristics of nanoscaled pMOSFETs for varying body biases. Both a reduced time-zero variability and a reduced time-dependent variability are observed when a forward body bias is applied. In order to explain these observations, a model based on the modulation of the number of unscreened dopant atoms within the channel depletion region is proposed.
{"title":"Reduction of the BTI time-dependent variability in nanoscaled MOSFETs by body bias","authors":"J. Franco, B. Kaczer, M. Toledano-Luque, P. Roussel, G. Groeseneken, B. Schwarz, M. Bina, M. Waltl, P. Wagner, T. Grasser","doi":"10.1109/IRPS.2013.6531958","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531958","url":null,"abstract":"We study the impact of individual charged gate oxide defects on the characteristics of nanoscaled pMOSFETs for varying body biases. Both a reduced time-zero variability and a reduced time-dependent variability are observed when a forward body bias is applied. In order to explain these observations, a model based on the modulation of the number of unscreened dopant atoms within the channel depletion region is proposed.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"38 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129154620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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