A mixed signal multiplier using A2 binary representation dedicated to neural networks applications

Abstract

The main goal of our work is to investigate the delay performances of redundant binary arithmetic operators using different CMOS logic and mixed signals styles. This paper presents a novel technique for A2 redundant binary multiplication in mixed-signal circuits especially for neural networks applications. The proposed multiplier consists of three cascaded blocks: Two 3-bit Arithmetic Multiplier Digital to Analog Converter (AMDAC) cells, and one 6-bit Flash ADC. Our technique indicates that this approach significantly reduces the silicon area occupied by such multipliers compared to the classical scheme using combinational multipliers. The circuit being studied is optimized for speed efficiency at 0.35μm CMOS process.