{"title":"Shallow multiplication circuits","authors":"M. Paterson, Uri Zwick","doi":"10.1109/ARITH.1991.145530","DOIUrl":null,"url":null,"abstract":"Y. Ofman (1963), C.S. Wallace (1964), and others used carry save adders to design multiplication circuits whose total delay is proportional to the logarithm of the length of two numbers multiplied. An extension of their work is presented. A general theory is presented describing the optimal way in which given carry save adders can be combined into carry save networks. Two new designs of basic carry save adders are described. Using these building blocks and the general theory, the shallowest known theoretical circuits for multiplication are obtained.<<ETX>>","PeriodicalId":190650,"journal":{"name":"[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic","volume":"76 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARITH.1991.145530","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
Y. Ofman (1963), C.S. Wallace (1964), and others used carry save adders to design multiplication circuits whose total delay is proportional to the logarithm of the length of two numbers multiplied. An extension of their work is presented. A general theory is presented describing the optimal way in which given carry save adders can be combined into carry save networks. Two new designs of basic carry save adders are described. Using these building blocks and the general theory, the shallowest known theoretical circuits for multiplication are obtained.<>
Y. Ofman (1963)， C.S. Wallace(1964)等人使用进位保存加法器设计乘法电路，其总延迟与两个数字相乘长度的对数成正比。介绍了他们工作的延伸。给出了将给定的进位保存加法器组合成进位保存网络的最优方法。介绍了两种新的基本进位存加器的设计。利用这些基本单元和一般理论，我们得到了已知最浅的乘法理论电路。
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