Fault Tolerant Arithmetic Operations with Multiple Error Detection and Correction

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI:10.1109/DFT.2007.56

M. Valinataj, S. Safari

引用次数: 18

Abstract

Emerging technologies are dealing with more complex VLSI systems, also smaller gates and transistors which are severely influenced by electromagnetic noises and single event transient (SET) errors. Because of this increase in sensitivity and decrease in size, several soft errors might appear at the same time which can lead to multiple simultaneous errors. In this paper a concurrent and multiple error detection and correction scheme is presented for adders and multipliers based on the combination of a parity prediction scheme and a partially distributed triple modular redundancy. This scheme fits carry look-ahead and carry-skip adders/ALUs in which the carry logic represents the largest part of the circuit. The efficiency of the scheme is basically analyzed by the probability computations. The simulation of multiple random fault injection is performed to validate the predicted performance.

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具有多重错误检测和纠错的容错算术运算

新兴技术正在处理更复杂的VLSI系统，以及受电磁噪声和单事件瞬态(SET)误差严重影响的更小的门和晶体管。由于灵敏度的增加和尺寸的减小，可能会同时出现几个软错误，从而导致多个同时错误。本文提出了一种基于奇偶预测和部分分布式三模冗余的加法器并发多重错误检测与纠错方案。该方案适用于进位前瞻和进位跳加器/ alu，其中进位逻辑占电路的最大部分。通过概率计算基本分析了该方案的有效性。通过对多个随机故障注入的仿真，验证了预测的性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)

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