Hidekazu Takahashi, M. Kinoshita, Kazumichi Morita, Takahiro Shirai, Toshiaki Sato, T. Kimura, H. Yuzurihara, S. Inoue
{"title":"A 3.9 /spl mu/m pixel pitch VGA format 10 b digital image sensor with 1.5-transistor/pixel","authors":"Hidekazu Takahashi, M. Kinoshita, Kazumichi Morita, Takahiro Shirai, Toshiaki Sato, T. Kimura, H. Yuzurihara, S. Inoue","doi":"10.1109/ISSCC.2004.1332617","DOIUrl":null,"url":null,"abstract":"A CMOS image sensor with a shared 1.5 transistor/pixel architecture and buried photodiode with complete charge transfer capability is described. The sensor achieves a 330 /spl mu/V noise floor and 50 pA/cm/sup 2/ dark current at 45/spl deg/C. The chip is fabricated in a thin planarized 0.35 /spl mu/m 1P2M CMOS process.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2004.1332617","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
A CMOS image sensor with a shared 1.5 transistor/pixel architecture and buried photodiode with complete charge transfer capability is described. The sensor achieves a 330 /spl mu/V noise floor and 50 pA/cm/sup 2/ dark current at 45/spl deg/C. The chip is fabricated in a thin planarized 0.35 /spl mu/m 1P2M CMOS process.