Pub Date : 2005-04-01DOI: 10.1093/ietele/e88-c.4.520
T. Seki, S. Akui, K. Seno, M. Nakai, T. Meguro, Tetsuo Kondo, A. Hashiguchi, Hirokazu Kawahara, K. Kumano, M. Shimura
A dynamic voltage and frequency management scheme that autonomously controls the clock frequency (8 to 123 MHz at 0.5 MHz step) and adaptively controls the voltage (0.9 to 1.6 V at 5 mV step) with a leakage power compensation effect is developed for a low-power embedded microprocessor. It achieves 82% power reduction in personal information manager (PIM) application.
{"title":"Dynamic voltage and frequency management for a low-power embedded microprocessor","authors":"T. Seki, S. Akui, K. Seno, M. Nakai, T. Meguro, Tetsuo Kondo, A. Hashiguchi, Hirokazu Kawahara, K. Kumano, M. Shimura","doi":"10.1093/ietele/e88-c.4.520","DOIUrl":"https://doi.org/10.1093/ietele/e88-c.4.520","url":null,"abstract":"A dynamic voltage and frequency management scheme that autonomously controls the clock frequency (8 to 123 MHz at 0.5 MHz step) and adaptively controls the voltage (0.9 to 1.6 V at 5 mV step) with a leakage power compensation effect is developed for a low-power embedded microprocessor. It achieves 82% power reduction in personal information manager (PIM) application.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124437730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/JSSC.2004.835644
Quan Le, Sang-Gug Lee, Y. Oh, Ho-Yong Kang, T. Yoo
A burst-mode receiver for 1.25 Gb/s Ethernet passive optical network (PON) systems is implemented in 0.18 /spl mu/m CMOS technology. With AGC, the receiver achieves a sensitivity of -22 dBm, overload of -3.5 dBm and loud/soft ratio of 17.5 dB. The receiver creates an internal reset signal, and all timing parameters exceed current standards.
{"title":"Burst-mode receiver for 1.25Gb/s Ethernet PON with AGC and internally created reset signal","authors":"Quan Le, Sang-Gug Lee, Y. Oh, Ho-Yong Kang, T. Yoo","doi":"10.1109/JSSC.2004.835644","DOIUrl":"https://doi.org/10.1109/JSSC.2004.835644","url":null,"abstract":"A burst-mode receiver for 1.25 Gb/s Ethernet passive optical network (PON) systems is implemented in 0.18 /spl mu/m CMOS technology. With AGC, the receiver achieves a sensitivity of -22 dBm, overload of -3.5 dBm and loud/soft ratio of 17.5 dB. The receiver creates an internal reset signal, and all timing parameters exceed current standards.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126250124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332805
Chia-Hsin Wu, Chang-Shun Liu, Shen-luan Liu
A fully integrated 2 GHz variable gain amplifier is implemented in a 0.18 /spl mu/m CMOS process to achieve 50 dB linear-in-magnitude controlled-gain range for 10GBase-LX4 Ethernet. The measured dynamic range is 35 dB from 9 to 495 mVpp with BER less than 10/sup -12/. The 0.7 mm/sup 2/ chip dissipates 40 mW.
{"title":"A 2 GHz CMOS variable-gain amplifier with 50 dB linear-in-magnitude controlled gain range for 10GBase-LX4 Ethernet","authors":"Chia-Hsin Wu, Chang-Shun Liu, Shen-luan Liu","doi":"10.1109/ISSCC.2004.1332805","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332805","url":null,"abstract":"A fully integrated 2 GHz variable gain amplifier is implemented in a 0.18 /spl mu/m CMOS process to achieve 50 dB linear-in-magnitude controlled-gain range for 10GBase-LX4 Ethernet. The measured dynamic range is 35 dB from 9 to 495 mVpp with BER less than 10/sup -12/. The 0.7 mm/sup 2/ chip dissipates 40 mW.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115411273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332766
R. Hogervorst, B. Tourette, N. Monier, O. Metayer, E. Afifi, J.-C. Delefosse, J. Michel
The analog front-end (AFE) for ADSL customer premise equipment (CPE) permits quad-spectrum down-stream (138 kHz to 3.75 MHz). The AFE includes a 5 V line driver in a standard 0.18 /spl mu/m 3 V CMOS process. The receive path contains an ADC with an 80 dB SNDR over 3.75 MHz bandwidth. Down-stream data rates of more than 50 Mb/s are measured on short loops.
{"title":"A 3 V CMOS quad-spectrum ADSL CPE analog front-end with 5 V integrated line driver","authors":"R. Hogervorst, B. Tourette, N. Monier, O. Metayer, E. Afifi, J.-C. Delefosse, J. Michel","doi":"10.1109/ISSCC.2004.1332766","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332766","url":null,"abstract":"The analog front-end (AFE) for ADSL customer premise equipment (CPE) permits quad-spectrum down-stream (138 kHz to 3.75 MHz). The AFE includes a 5 V line driver in a standard 0.18 /spl mu/m 3 V CMOS process. The receive path contains an ADC with an 80 dB SNDR over 3.75 MHz bandwidth. Down-stream data rates of more than 50 Mb/s are measured on short loops.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116690554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332735
K. Nose, M. Mizuno
The realization of SoCs operating at 10GHz and multiple frequency IP-cores is possible using parallel clocking. With 2.5GHz 4-phase parallel clocking, the skew reduction circuits and multi-phase flip-flops successfully operate at 10GHz.
{"title":"Parallel clocking: a multi-phase clock-network for 10GHz SoC","authors":"K. Nose, M. Mizuno","doi":"10.1109/ISSCC.2004.1332735","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332735","url":null,"abstract":"The realization of SoCs operating at 10GHz and multiple frequency IP-cores is possible using parallel clocking. With 2.5GHz 4-phase parallel clocking, the skew reduction circuits and multi-phase flip-flops successfully operate at 10GHz.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126131335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332762
S. Otaka, M. Ashida, M. Ishii, T. Itakura
A 3rd-order intermodulation (IM3) cancellation technique using a sub-mixer is proposed for low-power, low-distortion mixers. The technique reduces IM3 by 18dB with a current increase of less than 10%. The mixer achieves an IIP3 of 10dBm, a gain of 8.7dB, a NF of 9.8dB and dissipates 30mW from 2.9V.
{"title":"A +110dBm IIP3 SiGe mixer with IM3 cancellation technique","authors":"S. Otaka, M. Ashida, M. Ishii, T. Itakura","doi":"10.1109/ISSCC.2004.1332762","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332762","url":null,"abstract":"A 3rd-order intermodulation (IM3) cancellation technique using a sub-mixer is proposed for low-power, low-distortion mixers. The technique reduces IM3 by 18dB with a current increase of less than 10%. The mixer achieves an IIP3 of 10dBm, a gain of 8.7dB, a NF of 9.8dB and dissipates 30mW from 2.9V.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126945023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332715
Eun-Chul Park, E. Yoon
A coupled distributed oscillator is designed using low-loss MEMS coupled transmission lines to achieve phase noise improvement of 7dB, and an additional 2dB improvement is attributed to the MEMS transmission lines. The oscillators are fabricated in a 0.18/spl mu/m 6M CMOS process, operate with a 1V supply and consume 26mW.
{"title":"A 13GHz CMOS distributed oscillator using MEMS coupled transmission lines for low phase noise","authors":"Eun-Chul Park, E. Yoon","doi":"10.1109/ISSCC.2004.1332715","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332715","url":null,"abstract":"A coupled distributed oscillator is designed using low-loss MEMS coupled transmission lines to achieve phase noise improvement of 7dB, and an additional 2dB improvement is attributed to the MEMS transmission lines. The oscillators are fabricated in a 0.18/spl mu/m 6M CMOS process, operate with a 1V supply and consume 26mW.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126963204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332772
Y. Adelman, D. Agur, T. Ben-Nun, O. Chalak, Z. Greenfield, R. Holzer, M. Jalfon, A. Kadry, E. Kraus, F. Lange, H. Meirov, A. Olofsson, O. Raikhman, D. Treves, S. Zur, R. Talmudi
A 600 MHz general-purpose DSP with 24 Mb of embedded DRAM, 154 GOPS, 4800 MMACS, and 40 Gb/s I/O throughput is presented. The chip contains over 60M transistors and is implemented in 0.13 /spl mu/m 8M CMOS technology.
{"title":"A 600 MHz DSP with 24 Mb embedded DRAM with an enhanced instruction set for wireless communication","authors":"Y. Adelman, D. Agur, T. Ben-Nun, O. Chalak, Z. Greenfield, R. Holzer, M. Jalfon, A. Kadry, E. Kraus, F. Lange, H. Meirov, A. Olofsson, O. Raikhman, D. Treves, S. Zur, R. Talmudi","doi":"10.1109/ISSCC.2004.1332772","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332772","url":null,"abstract":"A 600 MHz general-purpose DSP with 24 Mb of embedded DRAM, 154 GOPS, 4800 MMACS, and 40 Gb/s I/O throughput is presented. The chip contains over 60M transistors and is implemented in 0.13 /spl mu/m 8M CMOS technology.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116155030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332621
G. Storm, J. Hurwitz, D. Renshaw, K. Findlater, R. Henderson, M. Purcell
A 352/spl times/288 pixel array achieves >120 dB dynamic range through merging sequential linear and logarithmic images. Calibration is used to match offset and gain. A 7-transistor pixel is built in a 0.18 /spl mu/m 1P4M CMOS process.
{"title":"Combined linear-logarithmic CMOS image sensor","authors":"G. Storm, J. Hurwitz, D. Renshaw, K. Findlater, R. Henderson, M. Purcell","doi":"10.1109/ISSCC.2004.1332621","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332621","url":null,"abstract":"A 352/spl times/288 pixel array achieves >120 dB dynamic range through merging sequential linear and logarithmic images. Calibration is used to match offset and gain. A 7-transistor pixel is built in a 0.18 /spl mu/m 1P4M CMOS process.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114591270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332620
Kwang-Hyun Lee, E. Yoon
A 512 /spl times/ 384 CMOS image sensor in 0.18/spl mu/m 1P4M technology with 5.9/spl mu/m pixel pitch and a dynamic reset current source to compensate for kTC reset noise and fixed pattern noise is presented. A total of 390/spl mu/V(rms) readout noise, and a factor of two improvement over conventional reset is achieved. The chip operates at 1.8V and consumes 40mW excluding I/O and off-chip DAC for a single-slope ADC at 24frames/s.
{"title":"A CMOS image sensor with reset level control using dynamic reset current source for noise suppression","authors":"Kwang-Hyun Lee, E. Yoon","doi":"10.1109/ISSCC.2004.1332620","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332620","url":null,"abstract":"A 512 /spl times/ 384 CMOS image sensor in 0.18/spl mu/m 1P4M technology with 5.9/spl mu/m pixel pitch and a dynamic reset current source to compensate for kTC reset noise and fixed pattern noise is presented. A total of 390/spl mu/V(rms) readout noise, and a factor of two improvement over conventional reset is achieved. The chip operates at 1.8V and consumes 40mW excluding I/O and off-chip DAC for a single-slope ADC at 24frames/s.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130367147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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