{"title":"A Highly Digital CCO-Based Asynchronous Analog-to-Time Converter","authors":"S. T. Chandrasekaran, A. Sanyal","doi":"10.1109/MWSCAS.2019.8885366","DOIUrl":null,"url":null,"abstract":"This paper presents an asynchronous current controlled oscillator (CCO) based analog-to-time converter (ATC). The proposed ATC uses a ring oscillator as phase-domain integrator and quantizer. A negative feedback loop using current steering digital-to-analog converter (DAC) relaxes linearity requirement of the CCO. The ATC output is a multi-phase pulse-width modulated (PWM) signal which can be used with continuous-time digital signal processing systems. The proposed ATC is simulated in 65nm CMOS process an√d has a 59.2dB SNDR with an input-referred noise of 42.6nV/$\\sqrt {{\\text{Hz}}} $ over 500kHz bandwidth while consuming 11µW from 0.5V power supply.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2019.8885366","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents an asynchronous current controlled oscillator (CCO) based analog-to-time converter (ATC). The proposed ATC uses a ring oscillator as phase-domain integrator and quantizer. A negative feedback loop using current steering digital-to-analog converter (DAC) relaxes linearity requirement of the CCO. The ATC output is a multi-phase pulse-width modulated (PWM) signal which can be used with continuous-time digital signal processing systems. The proposed ATC is simulated in 65nm CMOS process an√d has a 59.2dB SNDR with an input-referred noise of 42.6nV/$\sqrt {{\text{Hz}}} $ over 500kHz bandwidth while consuming 11µW from 0.5V power supply.
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