{"title":"Reduction of the Feedback Capacitance of HFETs by Changing Transistor Layout and Using Via Holes for Source Grounding","authors":"N. Rorsman, M. Garcia, C. Karlsson, H. Zirath","doi":"10.1109/EUMA.1994.337303","DOIUrl":null,"url":null,"abstract":"The influence of HFET layout and via holes on the feedback capacitance of passive and non-gated as well as active HFETs has been examined. We have found that by careful design of the layout of the HFET and using via-hole for source grounding it is possible to reduce the feedback capacitance, thus improving the high frequency characteristics of the HFET. The total feedback capacitance was reduced by 70 % for a passive device with via holes and by varying one layout parameter. Results on active InP-based HFETs without via-holes show a total decrease of the feedback capacitance of 40 % for an InAlAs/InGaAs/InP HFET. The maximum stable gain at 40 GHz for an InAlAs/InGaAs/InP HFET. Was increased by 1.5 dB by changing the layout.","PeriodicalId":440371,"journal":{"name":"1994 24th European Microwave Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1994 24th European Microwave Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EUMA.1994.337303","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
The influence of HFET layout and via holes on the feedback capacitance of passive and non-gated as well as active HFETs has been examined. We have found that by careful design of the layout of the HFET and using via-hole for source grounding it is possible to reduce the feedback capacitance, thus improving the high frequency characteristics of the HFET. The total feedback capacitance was reduced by 70 % for a passive device with via holes and by varying one layout parameter. Results on active InP-based HFETs without via-holes show a total decrease of the feedback capacitance of 40 % for an InAlAs/InGaAs/InP HFET. The maximum stable gain at 40 GHz for an InAlAs/InGaAs/InP HFET. Was increased by 1.5 dB by changing the layout.
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