H. Tanizaki, T. Tsuji, J. Otani, Y. Yamaguchi, Y. Murai, H. Furuta, S. Ueno, T. Oishi, M. Hayashikoshi, H. Hidaka
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引用次数: 36
Abstract
A high-density and high-speed memory cell named 1-transistor 4-magnetic tunnel junction (1T-4MTJ) has been proposed for magnetic random access memory (MRAM). The new 1T-4MTJ cell has been successfully demonstrated by a 1 Mb MRAM test device, using a 130 nm CMOS process. The sensing scheme of a self-reference sense amplifier with Voltage offset (SRSV) enables high-speed memory operation (access time) of tAC=56 nsec and 50 MHz@4cycle.
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