A semantic model of VHDL for validating rewriting algebras

Abstract

This paper presents a formal model of the dynamic semantics of VHDL using interval temporal logic. The model uses a declarative style that provides a semantic definition of VHDL independent of the VHDL simulation cycle. Therefore, the model can be used as a platform for comparing alternative and possibly more efficient algorithms for simulating VHDL. Furthermore, optimization techniques for improving the performance of VHDL simulators can be validated against this model. To support this claim we present a proof asserting the validity of process-folding. In contrast to past efforts that concentrate only on design verification, this model is also oriented towards CAD tool optimization. The model is comprehensive and characterizes most of the important features of elaborated VHDL.