Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546491
E. Biersack, Frédéric Thiesse
We consider the admission control problem in video servers for the retrieval of media data from disk storage. We assume that the I/O bandwidth of the server disk is limited. Given a certain I/O bandwidth, admission control decides whether or not a new client can be accepted without affecting the quality of service promised to the already admitted clients. Assuming variable bit rate (VBR) video streams, we consider an admission control policy with both, deterministic and statistical service guarantees for constant time length retrieval (CTL) and evaluate its performance in terms of the number of clients admitted.
{"title":"Statistical admission control in video servers with variable bit rate streams and constant time length retrieval","authors":"E. Biersack, Frédéric Thiesse","doi":"10.1109/EURMIC.1996.546491","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546491","url":null,"abstract":"We consider the admission control problem in video servers for the retrieval of media data from disk storage. We assume that the I/O bandwidth of the server disk is limited. Given a certain I/O bandwidth, admission control decides whether or not a new client can be accepted without affecting the quality of service promised to the already admitted clients. Assuming variable bit rate (VBR) video streams, we consider an admission control policy with both, deterministic and statistical service guarantees for constant time length retrieval (CTL) and evaluate its performance in terms of the number of clients admitted.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125185816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546379
S. L. Pandey, Kothanda R. Subramanian, P. Wilsey
This paper presents a formal model of the dynamic semantics of VHDL using interval temporal logic. The model uses a declarative style that provides a semantic definition of VHDL independent of the VHDL simulation cycle. Therefore, the model can be used as a platform for comparing alternative and possibly more efficient algorithms for simulating VHDL. Furthermore, optimization techniques for improving the performance of VHDL simulators can be validated against this model. To support this claim we present a proof asserting the validity of process-folding. In contrast to past efforts that concentrate only on design verification, this model is also oriented towards CAD tool optimization. The model is comprehensive and characterizes most of the important features of elaborated VHDL.
{"title":"A semantic model of VHDL for validating rewriting algebras","authors":"S. L. Pandey, Kothanda R. Subramanian, P. Wilsey","doi":"10.1109/EURMIC.1996.546379","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546379","url":null,"abstract":"This paper presents a formal model of the dynamic semantics of VHDL using interval temporal logic. The model uses a declarative style that provides a semantic definition of VHDL independent of the VHDL simulation cycle. Therefore, the model can be used as a platform for comparing alternative and possibly more efficient algorithms for simulating VHDL. Furthermore, optimization techniques for improving the performance of VHDL simulators can be validated against this model. To support this claim we present a proof asserting the validity of process-folding. In contrast to past efforts that concentrate only on design verification, this model is also oriented towards CAD tool optimization. The model is comprehensive and characterizes most of the important features of elaborated VHDL.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115986222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546395
Yong Sun, Hongji Yang
When specifying and designing computer network protocols, it is convenient to use an abstract synchronous communication mechanism. In practice, however, asynchronous communication mechanisms cannot be avoided. This paper presents a formal approach, based on Hoare's Communicating Sequential Processes (1985) and some other theoretical results on the specification and design of protocols which ensure the correctness of the protocols regardless of the communication mechanism used in implementation. The Alternating Bit protocol is used to illustrate our results.
{"title":"Communication mechanism independent protocol specification based on CSP: a case study","authors":"Yong Sun, Hongji Yang","doi":"10.1109/EURMIC.1996.546395","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546395","url":null,"abstract":"When specifying and designing computer network protocols, it is convenient to use an abstract synchronous communication mechanism. In practice, however, asynchronous communication mechanisms cannot be avoided. This paper presents a formal approach, based on Hoare's Communicating Sequential Processes (1985) and some other theoretical results on the specification and design of protocols which ensure the correctness of the protocols regardless of the communication mechanism used in implementation. The Alternating Bit protocol is used to illustrate our results.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124382920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546468
K. Ghose, Kiran Raghavendra Desai, P. Kogge
The implementation of dynamically bound object oriented programming languages require the ability to quickly bind a logical reference to a method and to quickly allocate a context for the invoked method. In this paper we examine how a method lookup cache (MLC) and a register windowing mechanism can speed up method binding and context allocation. We also show how the MLC can be incorporated into a contemporary pipelined datapath. A detailed register level simulation of the proposed scheme, driven by a set of fairly intensive object-oriented applications, show that a relatively small method lookup cache with only 64 or 128 entries reduces the average execution time of the applications by about 50%. With register windowing and the MLC, execution time reduces by 76% to 87% with respect to the base machine.
{"title":"Using method lookup caches and register windowing to speed up dynamically-bound object-oriented applications","authors":"K. Ghose, Kiran Raghavendra Desai, P. Kogge","doi":"10.1109/EURMIC.1996.546468","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546468","url":null,"abstract":"The implementation of dynamically bound object oriented programming languages require the ability to quickly bind a logical reference to a method and to quickly allocate a context for the invoked method. In this paper we examine how a method lookup cache (MLC) and a register windowing mechanism can speed up method binding and context allocation. We also show how the MLC can be incorporated into a contemporary pipelined datapath. A detailed register level simulation of the proposed scheme, driven by a set of fairly intensive object-oriented applications, show that a relatively small method lookup cache with only 64 or 128 entries reduces the average execution time of the applications by about 50%. With register windowing and the MLC, execution time reduces by 76% to 87% with respect to the base machine.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128016240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546456
G. Hayek, C. Robach
Up to now, strategies for behavioral fault modeling and testing are based on an adaptation of the gate-level strategies to generate test data at the behavioral level. In other words, they explore the impact of low-level faults on the behavioral fault modeling and detection. In this paper, we explore the dual approach, i.e. the impact of high-level fault detection on gate-level fault detection. Due to the great development of both design automation tools and hardware description languages such as VHDL or VERILOG which allow to specify a hardware system as a software program, behavioral faults are considered as software faults and the mutation-based testing, originally proposed to test software programs, is adapted to generate test data for VHDL descriptions. The generated test set is used to validate the VHDL description, seen as a software program, against (software) design faults as well as its hardware implementation against hardware faults. To validate the approach, the gate-level fault coverage of the generated test set is computed and compared to traditional ATPG's result.
{"title":"On the adequacy of deriving hardware test data from the behavioral specification","authors":"G. Hayek, C. Robach","doi":"10.1109/EURMIC.1996.546456","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546456","url":null,"abstract":"Up to now, strategies for behavioral fault modeling and testing are based on an adaptation of the gate-level strategies to generate test data at the behavioral level. In other words, they explore the impact of low-level faults on the behavioral fault modeling and detection. In this paper, we explore the dual approach, i.e. the impact of high-level fault detection on gate-level fault detection. Due to the great development of both design automation tools and hardware description languages such as VHDL or VERILOG which allow to specify a hardware system as a software program, behavioral faults are considered as software faults and the mutation-based testing, originally proposed to test software programs, is adapted to generate test data for VHDL descriptions. The generated test set is used to validate the VHDL description, seen as a software program, against (software) design faults as well as its hardware implementation against hardware faults. To validate the approach, the gate-level fault coverage of the generated test set is computed and compared to traditional ATPG's result.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132894036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546485
Jocelyne Farhat-Gissler, I. Demeure
We have proposed a scheduling framework for the development and support of applications that must meet temporal Quality of Service (QoS) constraints. This paper develops a case study: a geostationary satellite application. We describe how the application threads are partitioned into finer grain (or elementary) threads to which QoS constraints are applied; how they are organized into dependency graphs; and how this decomposition as well as, the dependency information and QoS constraints required on the application are exploited by a cooperative scheduling system. We demonstrate this by presenting illustrative scheduling scenarios of the chosen application.
{"title":"Automatic scheduling of applications with temporal QoS constraints: a case study","authors":"Jocelyne Farhat-Gissler, I. Demeure","doi":"10.1109/EURMIC.1996.546485","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546485","url":null,"abstract":"We have proposed a scheduling framework for the development and support of applications that must meet temporal Quality of Service (QoS) constraints. This paper develops a case study: a geostationary satellite application. We describe how the application threads are partitioned into finer grain (or elementary) threads to which QoS constraints are applied; how they are organized into dependency graphs; and how this decomposition as well as, the dependency information and QoS constraints required on the application are exploited by a cooperative scheduling system. We demonstrate this by presenting illustrative scheduling scenarios of the chosen application.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114796357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546462
A. Tentov, A. Grnarov
In this paper, a mathematical method for analysis of synchronous packet-switching interconnection networks with finite buffering capacity at the output of switching elements is presented. The proposed mathematical method is general in that it analyzed interconnection networks under uniform and nonuniform traffic with blocking. The existing methods for analysis of buffered interconnection networks have assumed either single or infinite buffers at each input (or output) port of a switch, as well as uniform traffic pattern of the networks. Firstly, in the paper a general model of synchronous buffered switching element, using output buffering, under assumption of finite buffer size for a very general class of traffic, is presented. Traffic can be uniform or nonuniform. It is assumed that the subsequent stages of the network are nearly independent and a model is extended for entire network under this assumption. Analytical results obtained with proposed model are then compared with each other and it is shown that the proposed mathematical method is more general then the known models of interconnection networks.
{"title":"Performance analysis of packet switching interconnection networks with finite buffers","authors":"A. Tentov, A. Grnarov","doi":"10.1109/EURMIC.1996.546462","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546462","url":null,"abstract":"In this paper, a mathematical method for analysis of synchronous packet-switching interconnection networks with finite buffering capacity at the output of switching elements is presented. The proposed mathematical method is general in that it analyzed interconnection networks under uniform and nonuniform traffic with blocking. The existing methods for analysis of buffered interconnection networks have assumed either single or infinite buffers at each input (or output) port of a switch, as well as uniform traffic pattern of the networks. Firstly, in the paper a general model of synchronous buffered switching element, using output buffering, under assumption of finite buffer size for a very general class of traffic, is presented. Traffic can be uniform or nonuniform. It is assumed that the subsequent stages of the network are nearly independent and a model is extended for entire network under this assumption. Analytical results obtained with proposed model are then compared with each other and it is shown that the proposed mathematical method is more general then the known models of interconnection networks.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129126089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546383
C. Siegelin, C. O'Donnell, U. Finger
This paper introduces a new approach to the implementation of event-driven multiprocessor simulators. Cache and memory behaviour is modelled through finite state machines which use a very limited amount of storage rather than a full execution context (CPU registers, stack). The resulting simulator design is conceptually simple and clean. Furthermore, we make the point that finite state machines can be scheduled faster. Our performance figures show that simulation overhead is lower than for comparable multiprocessor simulators.
{"title":"Efficient simulation of multiprocessors through finite state machines","authors":"C. Siegelin, C. O'Donnell, U. Finger","doi":"10.1109/EURMIC.1996.546383","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546383","url":null,"abstract":"This paper introduces a new approach to the implementation of event-driven multiprocessor simulators. Cache and memory behaviour is modelled through finite state machines which use a very limited amount of storage rather than a full execution context (CPU registers, stack). The resulting simulator design is conceptually simple and clean. Furthermore, we make the point that finite state machines can be scheduled faster. Our performance figures show that simulation overhead is lower than for comparable multiprocessor simulators.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131341072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546374
A. Antonov, V. Voevodin
The paper shows an application of the so-called V-Ray Technology for optimizing the TRFD and FLO52 Perfect Club Benchmarks to CRAY Y-MP and CRAY T3D supercomputers. We also discuss briefly the process of the determination of the potential parallelism of programs within V-Ray since this part of the technology played the key role for the successful optimization of the codes.
{"title":"Application of the V-Ray technology for optimization of the TRFD and FL052 Perfect Club Benchmarks to CRAY Y-MP and CRAY T3D supercomputers","authors":"A. Antonov, V. Voevodin","doi":"10.1109/EURMIC.1996.546374","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546374","url":null,"abstract":"The paper shows an application of the so-called V-Ray Technology for optimizing the TRFD and FLO52 Perfect Club Benchmarks to CRAY Y-MP and CRAY T3D supercomputers. We also discuss briefly the process of the determination of the potential parallelism of programs within V-Ray since this part of the technology played the key role for the successful optimization of the codes.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116053345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546382
B. Antal, G. Csertán, I. Majzik, A. Bondavalli, L. Simoncini
The need of efficient implementation, safety and performance requires early validation in the design of computer control systems. The detailed timing and reachability analysis in the development process is particularly important if we design equipments or algorithms of high performance and availability. In this paper we present a case study related to the early validation of control systems modeled by data flow networks. The model is validated indirectly as it is transformed to Petri nets in order to be able to utilize the tools available for Petri nets.
{"title":"Reachability and timing analysis in data flow networks: a case study","authors":"B. Antal, G. Csertán, I. Majzik, A. Bondavalli, L. Simoncini","doi":"10.1109/EURMIC.1996.546382","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546382","url":null,"abstract":"The need of efficient implementation, safety and performance requires early validation in the design of computer control systems. The detailed timing and reachability analysis in the development process is particularly important if we design equipments or algorithms of high performance and availability. In this paper we present a case study related to the early validation of control systems modeled by data flow networks. The model is validated indirectly as it is transformed to Petri nets in order to be able to utilize the tools available for Petri nets.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123884767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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