Measuring the effectiveness of symmetric and asymmetric transistor sizing for Single Event Transient mitigation in CMOS 90nm technologies

Abstract

Transistor sizing is a well-known technique to reduce Single Event Transients in nanometer technologies. In this work, the transistor sizing technique is evaluated at a 90nm 3D device model for SET robustness. Mix-mode simulations at TCAD were performed in three basic logic gates of the ST 90nm standard cell library. Results indicate that the transistor sizing can be more or less efficient to reduce SET according to the collected charge. For alpha particles, the technique can enhance the reliability for high transistor width sizes, while for high-energy particles the technique can increase the transient pulse amplitude and duration making SET effect even worse.