Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813812
C. Argyrides, C. Lisbôa, D. Pradhan, L. Carro
A low delay overhead technique for the correction of errors affecting sorting algorithms, based on the use of Hamming code, is presented. Given the number of values to be sorted the expected Hamming check bits (as SUMs) are calculated, and a checker technique performs single error correction with lower delay overhead than classic approaches based on algorithm redundancy. The proposed technique has been applied to the well known bubble sorting with different sets of values to be sorted and the comparison of the resulting overhead with that imposed by the classic duplication with comparison and triple modular redundancy techniques shows that it requires lower delay overhead while providing enhanced error correction capabilities.
{"title":"Single element correction in sorting algorithms with minimum delay overhead","authors":"C. Argyrides, C. Lisbôa, D. Pradhan, L. Carro","doi":"10.1109/LATW.2009.4813812","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813812","url":null,"abstract":"A low delay overhead technique for the correction of errors affecting sorting algorithms, based on the use of Hamming code, is presented. Given the number of values to be sorted the expected Hamming check bits (as SUMs) are calculated, and a checker technique performs single error correction with lower delay overhead than classic approaches based on algorithm redundancy. The proposed technique has been applied to the well known bubble sorting with different sets of values to be sorted and the comparison of the resulting overhead with that imposed by the classic duplication with comparison and triple modular redundancy techniques shows that it requires lower delay overhead while providing enhanced error correction capabilities.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117138151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813820
Eduardo Ribeiro da Silva, F. Costa, F. Behrens, Remerson Stein Kickhofel, R. Maltione
The impressive development of RF communications observed last years with the intensive use of RF modules in several Mixed Signal Integrated Circuit as well as industrial and automotive qualification process, requiring engaged products compliant with aggressive EMC standards, introduces a challenge on the IC fault analysis. This work discuss a cost effective solution, small die size area using a Mixed Signal Test Bus Interface (Analog Test Bus more Digital Wrapper) aimed at small and medium complexity ICs. The proposed approach provides a powerful real time debug channel for RFI fault analysis and internal failure mechanism identification. This architecture was implemented in a silicon test vehicle, 0.25u BiCMOS technology, where measurements and results are presented and discussed.
{"title":"Using mixed-mode test bus architecture to RF-based fault injection analysis and EMC fault debug","authors":"Eduardo Ribeiro da Silva, F. Costa, F. Behrens, Remerson Stein Kickhofel, R. Maltione","doi":"10.1109/LATW.2009.4813820","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813820","url":null,"abstract":"The impressive development of RF communications observed last years with the intensive use of RF modules in several Mixed Signal Integrated Circuit as well as industrial and automotive qualification process, requiring engaged products compliant with aggressive EMC standards, introduces a challenge on the IC fault analysis. This work discuss a cost effective solution, small die size area using a Mixed Signal Test Bus Interface (Analog Test Bus more Digital Wrapper) aimed at small and medium complexity ICs. The proposed approach provides a powerful real time debug channel for RFI fault analysis and internal failure mechanism identification. This architecture was implemented in a silicon test vehicle, 0.25u BiCMOS technology, where measurements and results are presented and discussed.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122407718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813798
M. Benabdenbi, F. Pêcheux, Etienne Faure
This paper introduces principles of software based on-line testing and monitoring of multi-processors systems on a chip (MPSoC).
介绍了基于软件的多处理器单片系统在线测试与监测的原理。
{"title":"On-line test and monitoring of multi-processor SoCs: A software-based approach","authors":"M. Benabdenbi, F. Pêcheux, Etienne Faure","doi":"10.1109/LATW.2009.4813798","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813798","url":null,"abstract":"This paper introduces principles of software based on-line testing and monitoring of multi-processors systems on a chip (MPSoC).","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"59 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132604364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813789
T. Assis, F. Kastensmidt, G. Wirth, R. Reis
Transistor sizing is a well-known technique to reduce Single Event Transients in nanometer technologies. In this work, the transistor sizing technique is evaluated at a 90nm 3D device model for SET robustness. Mix-mode simulations at TCAD were performed in three basic logic gates of the ST 90nm standard cell library. Results indicate that the transistor sizing can be more or less efficient to reduce SET according to the collected charge. For alpha particles, the technique can enhance the reliability for high transistor width sizes, while for high-energy particles the technique can increase the transient pulse amplitude and duration making SET effect even worse.
{"title":"Measuring the effectiveness of symmetric and asymmetric transistor sizing for Single Event Transient mitigation in CMOS 90nm technologies","authors":"T. Assis, F. Kastensmidt, G. Wirth, R. Reis","doi":"10.1109/LATW.2009.4813789","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813789","url":null,"abstract":"Transistor sizing is a well-known technique to reduce Single Event Transients in nanometer technologies. In this work, the transistor sizing technique is evaluated at a 90nm 3D device model for SET robustness. Mix-mode simulations at TCAD were performed in three basic logic gates of the ST 90nm standard cell library. Results indicate that the transistor sizing can be more or less efficient to reduce SET according to the collected charge. For alpha particles, the technique can enhance the reliability for high transistor width sizes, while for high-energy particles the technique can increase the transient pulse amplitude and duration making SET effect even worse.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116017530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813809
T. Weber, Juliano Cardoso Vacaro, T. Siqueira, Ingrid Jansch-Pôrto
Fault injection is an efficient technique to evaluate the robustness of computer systems and their fault tolerance strategies. In order to obtain accurate results from fault injection based tests, it is important to mimic real conditions during a test campaign. When testing dependability attributes of network applications the real faulty behavior of networks must be closely emulated. We show how probability distributions can be used to inject communication faults that closely resemble the behavior observed in real network environments. To demonstrate the strengths of this strategy we develop a reusable and extensible entity called FIEND, integrate it to a fault injector and use the resulting tool to run test experiments injecting non-uniform distributed faults in a network application taken as example.
{"title":"Generating non-uniform distributions for fault injection to emulate real network behavior in test campaigns","authors":"T. Weber, Juliano Cardoso Vacaro, T. Siqueira, Ingrid Jansch-Pôrto","doi":"10.1109/LATW.2009.4813809","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813809","url":null,"abstract":"Fault injection is an efficient technique to evaluate the robustness of computer systems and their fault tolerance strategies. In order to obtain accurate results from fault injection based tests, it is important to mimic real conditions during a test campaign. When testing dependability attributes of network applications the real faulty behavior of networks must be closely emulated. We show how probability distributions can be used to inject communication faults that closely resemble the behavior observed in real network environments. To demonstrate the strengths of this strategy we develop a reusable and extensible entity called FIEND, integrate it to a fault injector and use the resulting tool to run test experiments injecting non-uniform distributed faults in a network application taken as example.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130868859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813794
José Peralta, Marcelo Costamagna, G. Peretti, E. Romero, C. Marqués
This paper proposes a new performance characterization for Oscillation-Based Test (OBT). The ability of OBT for detecting deviation faults under simultaneous statistical fluctuation of the non-faulty parameters is evaluated. For this purpose, we use Monte Carlo simulations and a fault model that considers as faulty only one component of the filter under test while the others components adopt random values obtained from their fault-free statistical distributions. The new data reported here show (for the filters under study) the presence of hard-to-test components and low fault coverage values for small deviation faults.
{"title":"Estimating the quality of Oscillation-Based Test for detecting parametric faults","authors":"José Peralta, Marcelo Costamagna, G. Peretti, E. Romero, C. Marqués","doi":"10.1109/LATW.2009.4813794","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813794","url":null,"abstract":"This paper proposes a new performance characterization for Oscillation-Based Test (OBT). The ability of OBT for detecting deviation faults under simultaneous statistical fluctuation of the non-faulty parameters is evaluated. For this purpose, we use Monte Carlo simulations and a fault model that considers as faulty only one component of the filter under test while the others components adopt random values obtained from their fault-free statistical distributions. The new data reported here show (for the filters under study) the presence of hard-to-test components and low fault coverage values for small deviation faults.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123160633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813805
Liana Silva, S. Soares
To constantly test software, in order to keep it as free as possible from defects, it is required to find and apply a testing approach that best fits the product under test. The variety of problems and the richness of existing approaches make the challenge to choose and plan for a better combination to reach desired quality level even harder. This paper introduces a case study that aims presenting different test coverage values according to the used approach. The context of our study considers the application of structure-based techniques on a Java ME software product line, which makes testing even more critical due to software complexity. In this work we present code coverage analysis and evaluation of main differences between data flow and control flow techniques, considering the use of a test tool and the reuse of test assets in different software versions from a software product line.
{"title":"Analyzing structure-based techniques for test coverage on a J2ME software product line","authors":"Liana Silva, S. Soares","doi":"10.1109/LATW.2009.4813805","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813805","url":null,"abstract":"To constantly test software, in order to keep it as free as possible from defects, it is required to find and apply a testing approach that best fits the product under test. The variety of problems and the richness of existing approaches make the challenge to choose and plan for a better combination to reach desired quality level even harder. This paper introduces a case study that aims presenting different test coverage values according to the used approach. The context of our study considers the application of structure-based techniques on a Java ME software product line, which makes testing even more critical due to software complexity. In this work we present code coverage analysis and evaluation of main differences between data flow and control flow techniques, considering the use of a test tool and the reuse of test assets in different software versions from a software product line.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132664032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813804
Lucieli Tolfo Beque, Thiago Dai Pra, É. Cota
Real-time operating systems (RTOS) are becoming quite common in embedded applications and its correct operation is crucial to ensure system quality and reliability. However, the test of this specialized software has been often neglected in the embedded software testing literature. This paper presents preliminary results on the testing of the exception handling routines in an embedded operating system (EOS). We first analyze what makes an EOS so difficult to test. Then, we present some experiments that will help to devise a test methodology for this specific software.
{"title":"Testing requirements for an embedded operating system: The exception handling case study","authors":"Lucieli Tolfo Beque, Thiago Dai Pra, É. Cota","doi":"10.1109/LATW.2009.4813804","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813804","url":null,"abstract":"Real-time operating systems (RTOS) are becoming quite common in embedded applications and its correct operation is crucial to ensure system quality and reliability. However, the test of this specialized software has been often neglected in the embedded software testing literature. This paper presents preliminary results on the testing of the exception handling routines in an embedded operating system (EOS). We first analyze what makes an EOS so difficult to test. Then, we present some experiments that will help to devise a test methodology for this specific software.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124913264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813810
T. Cardoso, J. Nacif, A. O. Fernandes, C. Coelho
Verification is one of the most critical stages in integrated circuit development. Given the current market conditions, a wise manner to improve verification results would be concentrating resources in error-prone modules. In this paper a novel method of attaching information to commit messages is introduced. Through the use of a simple and parseable language, important and more accurate statistics can be retrieved. Tools were developed in order to make commits faster and prevent erroneous data analysis.
{"title":"BugTracer: A system for integrated circuit development tracking and statistics retrieval","authors":"T. Cardoso, J. Nacif, A. O. Fernandes, C. Coelho","doi":"10.1109/LATW.2009.4813810","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813810","url":null,"abstract":"Verification is one of the most critical stages in integrated circuit development. Given the current market conditions, a wise manner to improve verification results would be concentrating resources in error-prone modules. In this paper a novel method of attaching information to commit messages is introduced. Through the use of a simple and parseable language, important and more accurate statistics can be retrieved. Tools were developed in order to make commits faster and prevent erroneous data analysis.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"1072 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116020349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-02DOI: 10.1109/LATW.2009.4813788
C. C. Menegotto, T. Weber, R. Weber
A methodology for dependability assessment of complex computer systems, such as fault tolerant grids, is presented in this paper. The methodology uses communication fault injection and was built by adapting a widely accepted approach for performance analysis. To demonstrate its applicability and usefulness, the methodology was applied to a third party grid platform using a fault injector we are developing. The paper reasons about the advantages of this methodology to perform fault injection campaigns in the prototype phase of a system.
{"title":"A practical methodology for experimental fault injection to test complex network-based systems","authors":"C. C. Menegotto, T. Weber, R. Weber","doi":"10.1109/LATW.2009.4813788","DOIUrl":"https://doi.org/10.1109/LATW.2009.4813788","url":null,"abstract":"A methodology for dependability assessment of complex computer systems, such as fault tolerant grids, is presented in this paper. The methodology uses communication fault injection and was built by adapting a widely accepted approach for performance analysis. To demonstrate its applicability and usefulness, the methodology was applied to a third party grid platform using a fault injector we are developing. The paper reasons about the advantages of this methodology to perform fault injection campaigns in the prototype phase of a system.","PeriodicalId":343240,"journal":{"name":"2009 10th Latin American Test Workshop","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124405718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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