Leakage Reduction for Domino Circuits in Sub-65nm Technologies

Abstract

With aggressive technology scaling, leakage power is fast becoming a significant component of the total power consumption of high-performance circuits. In this paper, we analyse the gate leakage and subthreshold leakage current characteristics of domino circuits and propose a circuit which reduces both gate and subthreshold leakage, and thus the overall leakage of sub-65 nm domino circuits. Simulation results based on 45 nm BSIM4 models show that the gate leakage, subthreshold leakage and overall leakage are reduced by up to 94%, 64% and 89% respectively, as compared to the conventional dual-Vt designs. The proposed circuit maintains the inputs, the dynamic node and the output node at logic high, to reduce the gate leakage. It reduces subthreshold leakage by enhancing the stack effect and source biasing effect.