{"title":"Applying adaptive temporal filtering for SET mitigation based on the propagation-delay of every logical path","authors":"Jose Eduardo Pereira Souza, F. Kastensmidt","doi":"10.1109/LATW.2012.6261257","DOIUrl":null,"url":null,"abstract":"This paper proposes the use of a programmable radiation hardened flip-flop to select the most appropriate delay in the SET temporal filtering for each flip-flop in a circuit. Each flip-flop can filter SETs by using different delays based on the propagation-delay of its logical path. The propagation-delay variances among multiple paths can be used to increase or reduce the delay of the SET filtering. In this way, a delay with a minimum performance impact can always be selected. This approach was validated by electrical simulations in a case-study circuit Different SET pulse widths were injected. Results have shown the efficiently of this technique to filter SETs and to tolerate SEUs in integrated circuits.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 13th Latin American Test Workshop (LATW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LATW.2012.6261257","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper proposes the use of a programmable radiation hardened flip-flop to select the most appropriate delay in the SET temporal filtering for each flip-flop in a circuit. Each flip-flop can filter SETs by using different delays based on the propagation-delay of its logical path. The propagation-delay variances among multiple paths can be used to increase or reduce the delay of the SET filtering. In this way, a delay with a minimum performance impact can always be selected. This approach was validated by electrical simulations in a case-study circuit Different SET pulse widths were injected. Results have shown the efficiently of this technique to filter SETs and to tolerate SEUs in integrated circuits.