Ground bounce in CMOS ASICs

Proceedings., Second Annual IEEE ASIC Seminar and Exhibit, Pub Date : 1989-09-25 DOI:10.1109/ASIC.1989.123224

D. Steele

引用次数: 1

Abstract

A study has been undertaken to investigate the ground bounce phenomena in CMOS ASICs (application-specific integrated circuits). A simple mathematical analysis was performed to help gain an intuitive understanding of the problem. SPICE simulations were then performed to build a more detailed model. The SPICE model allowed different problem solving approaches to be compared in a straightforward manner. Laboratory experiments were performed to confirm the validity of the simulation and mathematical analyses. The results indicate that there are effective measures which can be taken to reduce the magnitude of voltage transients induced by the device and to minimize the device's sensitivity to ground bounce.<>

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CMOS asic中的地反弹

本文对CMOS专用集成电路中的地弹跳现象进行了研究。进行了简单的数学分析，以帮助直观地理解这个问题。然后进行SPICE模拟以建立更详细的模型。SPICE模型允许以一种直接的方式比较不同的问题解决方法。通过室内实验验证了仿真和数学分析的有效性。结果表明，可以采取有效的措施来减小器件引起的电压瞬变幅度，并使器件对地弹跳的灵敏度降到最低。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,

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