Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123168
T. Lyon
Recent developments in ECL (emitter-coupled logic) circuit technology have led to a new generation of high-density and higher-performance gate arrays. The choice of an ECL ASIC (application-specific integrated circuit) technology is discussed with regard to the use of proven versus new technology, ASIC benchmarks, and second sourcing. Design issues considered are the optimization of density and performance, power limits, estimated versus actual interconnect delays, pulse shrinkage and clocking, packaging, and cooling.<>
{"title":"High density and high performance ECL: some design tips","authors":"T. Lyon","doi":"10.1109/ASIC.1989.123168","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123168","url":null,"abstract":"Recent developments in ECL (emitter-coupled logic) circuit technology have led to a new generation of high-density and higher-performance gate arrays. The choice of an ECL ASIC (application-specific integrated circuit) technology is discussed with regard to the use of proven versus new technology, ASIC benchmarks, and second sourcing. Design issues considered are the optimization of density and performance, power limits, estimated versus actual interconnect delays, pulse shrinkage and clocking, packaging, and cooling.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126710429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123206
D. Pasternak, T. Hike
Software development and system integration in designs with microprocessors and microcontrollers is often accomplished with the aid of an in-circuit-emulator (ICE). Designs incorporating an architectural microcontroller core cell and peripheral cells embedded in an application-specific integrated circuit (ASIC) present additional challenges in software development and system integration. A description is given of the ASIC UCS51 family and a fully functional ICE that supports it. The core and peripheral cells are emulated with multiple ICs, and the user logic is emulated with programmable logic devices. Results of the first customer application and use are included.<>
{"title":"In-circuit-emulation in ASIC architectural core designs","authors":"D. Pasternak, T. Hike","doi":"10.1109/ASIC.1989.123206","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123206","url":null,"abstract":"Software development and system integration in designs with microprocessors and microcontrollers is often accomplished with the aid of an in-circuit-emulator (ICE). Designs incorporating an architectural microcontroller core cell and peripheral cells embedded in an application-specific integrated circuit (ASIC) present additional challenges in software development and system integration. A description is given of the ASIC UCS51 family and a fully functional ICE that supports it. The core and peripheral cells are emulated with multiple ICs, and the user logic is emulated with programmable logic devices. Results of the first customer application and use are included.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114360035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123228
R. Bowman
An object-oriented imaging model that automatically generates the physical layout of commonly used analog circuit macrocells based on input from an annotated net list is discussed. It provides information on constructed cells sufficient for parasitic element extraction. the imaging model is technology independent within fundamental process families (CMOS, bipolar, etc.) and currently includes a library of CMOS analog macrocells and associated physical templates. Templates are described by synthesis rules and graphics operators for two-dimensional shape generation.<>
{"title":"Analog macrocell layout generation","authors":"R. Bowman","doi":"10.1109/ASIC.1989.123228","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123228","url":null,"abstract":"An object-oriented imaging model that automatically generates the physical layout of commonly used analog circuit macrocells based on input from an annotated net list is discussed. It provides information on constructed cells sufficient for parasitic element extraction. the imaging model is technology independent within fundamental process families (CMOS, bipolar, etc.) and currently includes a library of CMOS analog macrocells and associated physical templates. Templates are described by synthesis rules and graphics operators for two-dimensional shape generation.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121573114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123239
R. L. Steinweg, M. Zampaglione, P. Lin
A flexible RAM compiler for gate arrays that is fully integrated into the user design tools is described. The various hardware and software features of the compiler are described, including variable aspect ratio with automatic selection, along with the design tool integration. The RAM compiled for minimum area came out with the 32 words in the core organized as 32 words down by one word across. It has a typical access time of about 10 ns. The RAM compiled for most square aspect ratio ended up with a core organization of 16 words down by 2 words across and an access time of about 8 ns. The RAM compiled for minimum access time has a core organization of 8 words down by 4 words across, and an access time of about 7 ns. If desired, other aspect ratio variations than those chosen automatically using the optimization criteria can be compiled by using the manual override option to specify the core organization directly.<>
{"title":"A user-configurable RAM compiler for gate arrays","authors":"R. L. Steinweg, M. Zampaglione, P. Lin","doi":"10.1109/ASIC.1989.123239","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123239","url":null,"abstract":"A flexible RAM compiler for gate arrays that is fully integrated into the user design tools is described. The various hardware and software features of the compiler are described, including variable aspect ratio with automatic selection, along with the design tool integration. The RAM compiled for minimum area came out with the 32 words in the core organized as 32 words down by one word across. It has a typical access time of about 10 ns. The RAM compiled for most square aspect ratio ended up with a core organization of 16 words down by 2 words across and an access time of about 8 ns. The RAM compiled for minimum access time has a core organization of 8 words down by 4 words across, and an access time of about 7 ns. If desired, other aspect ratio variations than those chosen automatically using the optimization criteria can be compiled by using the manual override option to specify the core organization directly.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129997251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123223
K. Wang, J. Chen
Incremental compilation is desirable to avoid recompiling a large network when only a few modules are modified. An algorithm that partitions a network in a hierarchical manner is described. The linker links together separately compiled or linked modules to generate machine codes for the IKOS hardware simulator. The machine codes generated for the duplicate subnetworks (or logic blocks) need not be reproduced and can be loaded to the simulator for the times of occurrences by adjusting for the base offsets.<>
{"title":"Incremental netlist compilation for IKOS hardware logic simulator","authors":"K. Wang, J. Chen","doi":"10.1109/ASIC.1989.123223","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123223","url":null,"abstract":"Incremental compilation is desirable to avoid recompiling a large network when only a few modules are modified. An algorithm that partitions a network in a hierarchical manner is described. The linker links together separately compiled or linked modules to generate machine codes for the IKOS hardware simulator. The machine codes generated for the duplicate subnetworks (or logic blocks) need not be reproduced and can be loaded to the simulator for the times of occurrences by adjusting for the base offsets.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"271 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134011205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123214
J. Vincent
A case study of the design of a timing generator ASIC (application-specific integrated circuit) for an NTSC-compatible imaging system is presented. The case history includes many of the classic problems in this type of design. Consideration is given to the problems of changing specifications during the design process, adding special functionality while minimizing testability enhancements, the pressure of timeliness, and the importance of thoroughly verifying every part of the design.<>
{"title":"Case study: an NTSC imaging system timing gate array design","authors":"J. Vincent","doi":"10.1109/ASIC.1989.123214","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123214","url":null,"abstract":"A case study of the design of a timing generator ASIC (application-specific integrated circuit) for an NTSC-compatible imaging system is presented. The case history includes many of the classic problems in this type of design. Consideration is given to the problems of changing specifications during the design process, adding special functionality while minimizing testability enhancements, the pressure of timeliness, and the importance of thoroughly verifying every part of the design.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116981233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123248
M.J.S. Smith, R. Jorgenson, C. Portmann, P. Tschang, C. Anagnostopoulos, R. Rao, P. Valdenaire, H. Ching
A VLSI program at the University of Hawaii initiated in 1987 is discussed. Since this time, the curriculum has been expanded to offer undergraduate classes in analog and digital VLSI design. The expansion and development of this new curriculum are described.<>
{"title":"Creation of an undergraduate curriculum in ASIC design","authors":"M.J.S. Smith, R. Jorgenson, C. Portmann, P. Tschang, C. Anagnostopoulos, R. Rao, P. Valdenaire, H. Ching","doi":"10.1109/ASIC.1989.123248","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123248","url":null,"abstract":"A VLSI program at the University of Hawaii initiated in 1987 is discussed. Since this time, the curriculum has been expanded to offer undergraduate classes in analog and digital VLSI design. The expansion and development of this new curriculum are described.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125909620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123209
J. Klein, R. Peyrard
To meet image analysis requirements in terms of processing speed and computing capacities, the authors have developed an ASIC (application-specific integrated circuit) with a programmable architecture, supporting the latest algorithms of mathematical morphology. Designed in 1.5- mu m CMOS technology, the ASIC can process 8-b images at a 20-MHz pixel frequency, in pipeline or in parallel. The architecture of PIMM1 is discussed, along with two multiprocessor organizations.<>
为了满足图像分析在处理速度和计算能力方面的要求，作者开发了一种具有可编程架构的专用集成电路(ASIC)，支持最新的数学形态学算法。ASIC采用1.5 μ m CMOS技术设计，可以处理20mhz像素频率的8-b图像，可以流水线或并行处理。讨论了PIMM1的体系结构，以及两个多处理器组织。
{"title":"PIMM1, an image processing ASIC based on mathematical morphology","authors":"J. Klein, R. Peyrard","doi":"10.1109/ASIC.1989.123209","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123209","url":null,"abstract":"To meet image analysis requirements in terms of processing speed and computing capacities, the authors have developed an ASIC (application-specific integrated circuit) with a programmable architecture, supporting the latest algorithms of mathematical morphology. Designed in 1.5- mu m CMOS technology, the ASIC can process 8-b images at a 20-MHz pixel frequency, in pipeline or in parallel. The architecture of PIMM1 is discussed, along with two multiprocessor organizations.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129343310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123167
J. A. Heise
A design experience with GaAs ASICs (application-specific integrated circuits) is presented from the user's point of view. Vendor selection criteria, design experience, board considerations, and testings are discussed in detail. It is shown that through the application of GaAs ASICs a much greater understanding of what is required to implement them into a system has been achieved. Generally, these requirements do not differ greatly from those of other technologies, but there are some important differences to consider. It is concluded that the greater speed, temperature range, and radiation tolerance of GaAs, combined with the functionality and space-saving of ASICs, justify the additional design time.<>
{"title":"GaAs ASIC design case study","authors":"J. A. Heise","doi":"10.1109/ASIC.1989.123167","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123167","url":null,"abstract":"A design experience with GaAs ASICs (application-specific integrated circuits) is presented from the user's point of view. Vendor selection criteria, design experience, board considerations, and testings are discussed in detail. It is shown that through the application of GaAs ASICs a much greater understanding of what is required to implement them into a system has been achieved. Generally, these requirements do not differ greatly from those of other technologies, but there are some important differences to consider. It is concluded that the greater speed, temperature range, and radiation tolerance of GaAs, combined with the functionality and space-saving of ASICs, justify the additional design time.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"07 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127261581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123166
A. Conoscenti
The state of the GaAs IC industry is summarized from an application-specific product perspective. Presently available products, packaging technology, applications, reliability, and future product directions are discussed.<>
{"title":"GaAs ASIC technology","authors":"A. Conoscenti","doi":"10.1109/ASIC.1989.123166","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123166","url":null,"abstract":"The state of the GaAs IC industry is summarized from an application-specific product perspective. Presently available products, packaging technology, applications, reliability, and future product directions are discussed.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132461440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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