Optimized surface mount structure for multi-Gigabit transmission

Abstract

This paper studies the impact of impedance discontinuity or mismatch contributed by surface mount (SMT) pads of AC coupling capacitor on Printed Circuit Board (PCB) traces with 26 Giga-bit per second (Gbps) transmission and the technique to minimize its adverse effect, which in turn mitigates the degradation of signal integrity. The design is optimized by the insertion of a cut-out on the reference plane area beneath the SMT pads. The impact of the optimization is studied for 0603 and 0402 package in 3D model extraction using EMPro software from Keysight, and simulations of s-parameter (i.e. insertion loss), time domain reflectometry (TDR) and eye diagram analysis are conducted using Advance Design System (ADS). Subsequently, the characterization using vector network analyzer (VNA) and bit error rate tester (BERT) is conducted on a prototype PCB to verify the correlation between the measurement and simulation.