ESD-ability Analysis of High Voltage nLDMOSs with the Drain-side Parasitic Schottky/Embedded STI

Abstract

In this paper, the Silvaco TCAD software is used to simulate the 0.18-μm 60V nLDMOS devices with drain-side parasitic Schottky device and embedded STIs. The modulation method is to divide the drain-side into two, four and six segments respectively and modulate in different arrangements. The TCAD simulations are performed at an input current of 1E-3 amps, and the lattice temperatures can be obtained. The high-voltage nLDMOS device will easily generate thermal runaway and other problems, causing the possibility of device damage. The appropriate width of STI on the drain-side can effectively isolate the high temperature generated by parasitic Schottky devices, and owing to the positive temperature coefficient effect of silicon, it will result in the final devcie excellent characteristics under an ESD event.