Digital dual mixer time difference for sub-nanosecond time synchronization in Ethernet

Abstract

A digital architecture for the Dual Mixer Time Difference (DMTD) is presented. This architecture has several advantages over other phase frequency detectors such as being linear, not having a dead zone and with an accuracy within the sub-picoseconds range. The intrinsic phase noise present in all timing signals is the main cause of the limitation in the accuracy of this phase frequency detector. Therefore, this paper describes the advantages and disadvantages of the presented architecture as well as how its performance changes with the clock phase noise by showing some experimental measurements. The application of this architecture, for the use of Ethernet as both data and synchronization network, is also discussed.