A 24-GHz low-noise amplifier co-designed with ESD protection using junction varactors in 65-nm RF CMOS

Abstract

By means of co-designed methodology, a 24-GHz low-noise amplifier, utilizing junction varactors as ESD protection, is first demonstrated by a 65-nm CMOS technology. The ESD protection capability of the junction varactors with multi-finger topology is characterized in details by transmission line pulse (TLP) measurements. Under a 1.2-V supply voltage and a 5.8-mA drain current, the proposed LNA achieves a 1.4-A TLP failure level, corresponding to an over 2-kV human body model (HBM) ESD protection. The LNA presents a lowest noise figure of 2.8 dB at 23.5 GHz and a peak power gain of 14.3 dB at 24 GHz, respectively. The input third-order intercept point (IIP3) is −5 dBm and the input and output return losses are both greater than 10 dB. To the best of our knowledge, this is the first attempt using junction varactors as the ESD device in 65-nm CMOS.