Pipelined block-lifting-based embedded processor for multiplying quaternions using distributed arithmetic

Abstract

This paper presents a systematic design of the of the integer-to-integer invertible quaternionic multiplier based on the block-lifting structure and pipelined embedded processor of the given multiplier using distributed arithmetic (DA) as a block of M-band linear phase paraunitary filter banks (LP PUFB) based on the quaternionic algebra (Q-PUFB) for the lossy-to-lossless image coding. A bank Q-PUFB based on the DA block-lifting structure reduces the number of rounding operations and has a regular layout. Since the block-lifting structures with rounding operations can implement the integer-to-integer transform (Q-PUFB).