A fully parallel-pipelined architecture for full-search block-based motion estimation

Abstract

The motion estimation block in the digital video encoder is the most important block and the most difficult block to design. The block-based motion estimation is simple technique for doing motion estimation and it is suitable for VLSI implementation. The full search block-based motion estimation suffers from the huge number of computations needed to look for the best match block among all the candidate blocks. To face this computation cost parallel and pipelined implementations are needed. This paper presents innovative parallel-pipelined architecture for full-search block-based motion estimation. Full search block matching algorithm is used in the proposed architecture. The proposed architecture has been prototyped, simulated and synthesized for 0.18 /spl mu/m CMOS technology using TSMC standard cells. Using 100 MHz clock frequency the proposed architecture needs 50.5 /spl mu/sec to compute the motion vectors, which enables processing of more than 10k frames per second. The prototyped architecture consumes 312.07 mW with 1.6 V supply voltage and has core area of 0.795 mm/sup 2/.