A 27.5–43.5 GHz high linearity up-conversion CMOS mixer for 5G communication

Abstract

A 27.5–43.5 GHz high linearity up-conversion mixer for 5G communication is designed and fabricated by standard 65 nm CMOS process. The mixer consists of a double balanced Gilbert cell and a linearized transconductance stage which is used to enhance the mixer linearity. In addition, based on the coupled resonators, the input and output baluns implement wide-band impedance matching. The mixer achieves IF-port input reflection coefficient less than −10 dB for frequency 9.7–17.8 GHz, and RF-port input reflection coefficient less than −10 dB for frequency 34.3 to 47.7 GHz. The conversion gain is −5 dB to −8 dB within 27.5–43.5 GHz. LO leakage to the IF port and RF port is less than −43 dB and −40 dB, respectively. The mixer realizes an output 1 dB compression point as high as 0.42 dBm at 38 GHz, while consuming 14 mW from a 1V supply.