Pub Date : 2017-12-16DOI: 10.1109/EDAPS.2017.8277051
Kyungjun Cho, Youngwoo Kim, Hyunsuk Lee, Gapyeol Park, Subin Kim, Kyungjune Son, Sumin Choi, Joungho Kim
Silicon interposer with high bandwidth memory (HBM) has been developed to achieve a terabyte/s bandwidth graphic card module. However, silicon interposer still has critical drawbacks regarding the complexity of fabrication and manufacturing cost. Especially, expensive through-silicon-via (TSV) process has become a serious problem for cost reduction. An innovative package substrate called embedded multi-die interconnect bridge (EMIB) becomes alternative solution for memory industries to reduce manufacturing cost and complexity of fabrication process of silicon interposer. Consequently, signal and power integrity (SI/PI) design and analysis of silicon based EMIB package substrate becomes essential, because it will be dominantly affected to HBM interface. In this paper, superior SI designs of EMIB is proposed and analyzed considering manufacturing cost. In addition, the impact on hierarchical PDN impedance due to EMIB is discussed and we proposed further direction for PI improvement. Proposed designs and analysis of EMIB package substrate are expected to be widely adopted in memory industries for next generation HBM interface.
{"title":"Signal and power integrity (SI/PI) analysis of heterogeneous integration using embedded multi-die interconnect bridge (EMIB) technology for high bandwidth memory (HBM)","authors":"Kyungjun Cho, Youngwoo Kim, Hyunsuk Lee, Gapyeol Park, Subin Kim, Kyungjune Son, Sumin Choi, Joungho Kim","doi":"10.1109/EDAPS.2017.8277051","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8277051","url":null,"abstract":"Silicon interposer with high bandwidth memory (HBM) has been developed to achieve a terabyte/s bandwidth graphic card module. However, silicon interposer still has critical drawbacks regarding the complexity of fabrication and manufacturing cost. Especially, expensive through-silicon-via (TSV) process has become a serious problem for cost reduction. An innovative package substrate called embedded multi-die interconnect bridge (EMIB) becomes alternative solution for memory industries to reduce manufacturing cost and complexity of fabrication process of silicon interposer. Consequently, signal and power integrity (SI/PI) design and analysis of silicon based EMIB package substrate becomes essential, because it will be dominantly affected to HBM interface. In this paper, superior SI designs of EMIB is proposed and analyzed considering manufacturing cost. In addition, the impact on hierarchical PDN impedance due to EMIB is discussed and we proposed further direction for PI improvement. Proposed designs and analysis of EMIB package substrate are expected to be widely adopted in memory industries for next generation HBM interface.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123944396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-15DOI: 10.1109/EDAPS.2017.8277017
Tao Shan, Wei Tang, Xunwang Dang, Maokun Li, Fan Yang, Shenheng Xu, Ji Wu
In this work, we investigated the feasibility of applying deep learning techniques to solve 2D Poisson's equation. A deep convolutional neural network is set up to predict the distribution of electric potential in 2D. With training data generated from a finite difference solver, the strong approximation capability of the deep convolutional neural network allows it to make correct prediction given information of the source and distribution of permittivity. Numerical experiments show that the predication error can reach below one percent, with a significant reduction in CPU time compared with the traditional solver based on finite difference methods.
{"title":"Study on a Poisson's equation solver based on deep learning technique","authors":"Tao Shan, Wei Tang, Xunwang Dang, Maokun Li, Fan Yang, Shenheng Xu, Ji Wu","doi":"10.1109/EDAPS.2017.8277017","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8277017","url":null,"abstract":"In this work, we investigated the feasibility of applying deep learning techniques to solve 2D Poisson's equation. A deep convolutional neural network is set up to predict the distribution of electric potential in 2D. With training data generated from a finite difference solver, the strong approximation capability of the deep convolutional neural network allows it to make correct prediction given information of the source and distribution of permittivity. Numerical experiments show that the predication error can reach below one percent, with a significant reduction in CPU time compared with the traditional solver based on finite difference methods.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128665094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276978
Dong Chen, Zhao Xing, Zhilin Chen, Chenxi Zhao, Huihua Liu, K. Kang
A CMOS package-level driver amplifier is presented. Since the inductor-less inter-stage matching network is utilized to enhance the bandwidth, the driver amplifier works from 0.72 ∼ 3.65 GHz with 134% relative bandwidth. Bonding wires for package are modeled using coupled lumped components and designed as parts of matching networks to enhance the power gain. The measured power gain is 27 dB with output referred P1dB is 8 dBm. The chip is fabricated in 65 nm CMOS technology, and ESD protection circuit is integrated. The size of the chip is 0.63 × 0.68 mm2.
{"title":"A package-level driver amplifier with 134% relative bandwidth","authors":"Dong Chen, Zhao Xing, Zhilin Chen, Chenxi Zhao, Huihua Liu, K. Kang","doi":"10.1109/EDAPS.2017.8276978","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276978","url":null,"abstract":"A CMOS package-level driver amplifier is presented. Since the inductor-less inter-stage matching network is utilized to enhance the bandwidth, the driver amplifier works from 0.72 ∼ 3.65 GHz with 134% relative bandwidth. Bonding wires for package are modeled using coupled lumped components and designed as parts of matching networks to enhance the power gain. The measured power gain is 27 dB with output referred P1dB is 8 dBm. The chip is fabricated in 65 nm CMOS technology, and ESD protection circuit is integrated. The size of the chip is 0.63 × 0.68 mm2.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120901146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276919
Hongjuan Wang, G. Han, Yan Liu, Jincheng Zhang, Y. Hao, Xiangwei Jiang
In this paper, we demonstrate the performance improvement in SiGeSn/GeSn p-channel hetero line-tunneling field-effect transistor (HL-TFET) via numerical simulation. The GeSn is located at the pocket region and forms the type-II staggered tunneling junction (TJ) that perpendicular to channel direction with the lattice-matched SiGeSn. The HL-TFET demonstrates the smaller onset voltage (VONSET), the higher on-state current (ION) and the steeper subthreshold swing (SS) in comparison with the GeSn homo Line TFET (L-TFET) and the conventional SiGeSn/GeSn double-gate hetero-TFET (H-TFET) devices. The performance enhancement is mainly owing to the larger tunneling area in HL-TFET attributing to the presence of heterojunction and the tunneling junction (TJ) that perpendicular to the channel direction.
{"title":"The performance improvement in SiGeSn/GeSn p-channel hetero Line Tunneling FET (HL-TFET)","authors":"Hongjuan Wang, G. Han, Yan Liu, Jincheng Zhang, Y. Hao, Xiangwei Jiang","doi":"10.1109/EDAPS.2017.8276919","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276919","url":null,"abstract":"In this paper, we demonstrate the performance improvement in SiGeSn/GeSn p-channel hetero line-tunneling field-effect transistor (HL-TFET) via numerical simulation. The GeSn is located at the pocket region and forms the type-II staggered tunneling junction (TJ) that perpendicular to channel direction with the lattice-matched SiGeSn. The HL-TFET demonstrates the smaller onset voltage (VONSET), the higher on-state current (ION) and the steeper subthreshold swing (SS) in comparison with the GeSn homo Line TFET (L-TFET) and the conventional SiGeSn/GeSn double-gate hetero-TFET (H-TFET) devices. The performance enhancement is mainly owing to the larger tunneling area in HL-TFET attributing to the presence of heterojunction and the tunneling junction (TJ) that perpendicular to the channel direction.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127306618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8277013
Qian Yang, B. Wei, Linqian Li, D. Ge
Outgoing waves can be strongly absorbed in Perfectly Matched Layer (PML), but its absorption effect strongly depends on the selection of the medium parameters in the PML layer. In this paper, the optimization problem of UPML absorption boundary of Discontinuous Galerkin Time Domain (DGTD) method based on 0.5 order and 1.5 order basis functions are studied. The effects of basis function, discrete scale, UPML layer thickness and medium parameters on the absorption effect are discussed in detail. Based on the simulation results, the optimized parameter selection scheme is given to simplify the choice of UPML.
{"title":"Selection of UPML parameters in DGTD calculation","authors":"Qian Yang, B. Wei, Linqian Li, D. Ge","doi":"10.1109/EDAPS.2017.8277013","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8277013","url":null,"abstract":"Outgoing waves can be strongly absorbed in Perfectly Matched Layer (PML), but its absorption effect strongly depends on the selection of the medium parameters in the PML layer. In this paper, the optimization problem of UPML absorption boundary of Discontinuous Galerkin Time Domain (DGTD) method based on 0.5 order and 1.5 order basis functions are studied. The effects of basis function, discrete scale, UPML layer thickness and medium parameters on the absorption effect are discussed in detail. Based on the simulation results, the optimized parameter selection scheme is given to simplify the choice of UPML.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127511603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276964
Guoxiao Cheng, Zhiqun Li, Lei Luo, Yan Yao, Xiao-Hu He, Boyong He
This paper presents a power amplifier (PA) for Ku-band T/R modules using 0.13-wm SiGe BiCMOS process technology with through-silicon-via (TSV). The proposed PA is composed of two cascode stages using high performance (HP) SiGe HBTs to achieve a high gain and a relatively high output power. The TSV is utilized to provide a low-resistance and low-inductance path to the ground. And the 3-D electro-magnetic (EM) simulation is applied to narrow the gap between the simulated and the measured results. The proposed PA achieves a small-signal gain of 27dB with a 3-dB bandwidth covering from 14.8GHz to 18.2GHz. The output 1dB compression point (OP1dB) and the peak power-added efficiency (PAE) are 21.4dBm and 16.7% at 15GHz respectively.
{"title":"Design of Ku-band SiGe-HBT power amplifier with through-silicon-via applying 3-D EM simulation","authors":"Guoxiao Cheng, Zhiqun Li, Lei Luo, Yan Yao, Xiao-Hu He, Boyong He","doi":"10.1109/EDAPS.2017.8276964","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276964","url":null,"abstract":"This paper presents a power amplifier (PA) for Ku-band T/R modules using 0.13-wm SiGe BiCMOS process technology with through-silicon-via (TSV). The proposed PA is composed of two cascode stages using high performance (HP) SiGe HBTs to achieve a high gain and a relatively high output power. The TSV is utilized to provide a low-resistance and low-inductance path to the ground. And the 3-D electro-magnetic (EM) simulation is applied to narrow the gap between the simulated and the measured results. The proposed PA achieves a small-signal gain of 27dB with a 3-dB bandwidth covering from 14.8GHz to 18.2GHz. The output 1dB compression point (OP1dB) and the peak power-added efficiency (PAE) are 21.4dBm and 16.7% at 15GHz respectively.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124935543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276961
Gong-Jin Li, Huashan Luan, Hong-li Peng, Jin Wang
A new Hilbert structure based EM meta-surface operated in 800–1000 MHz, is firstly presented in this paper for improving the isolation and radiation performance of a two-element antenna array. To verify the validity of our design, both the simulation and measurement are then carried out. Finally, their well-agreed results show that the isolation is increased by 5dB without degrading their radiating performance, making the design a good candidate for car wireless system applications.
{"title":"A new hilbert structure based meta-surface for improving isolation between two antenna elements","authors":"Gong-Jin Li, Huashan Luan, Hong-li Peng, Jin Wang","doi":"10.1109/EDAPS.2017.8276961","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276961","url":null,"abstract":"A new Hilbert structure based EM meta-surface operated in 800–1000 MHz, is firstly presented in this paper for improving the isolation and radiation performance of a two-element antenna array. To verify the validity of our design, both the simulation and measurement are then carried out. Finally, their well-agreed results show that the isolation is increased by 5dB without degrading their radiating performance, making the design a good candidate for car wireless system applications.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125091664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8277052
Jiamei Lv, J. Wen, Long Wang, Qingping Zhang, Yonghe Wang
Continuous variable attenuator with wide bandwidth has been designed and fabricated in a 65nm CMOS process. This π-type with three shunt FETs in one side demonstrates state-of-the art performance showing a minimum insertion loss of 0.13–2.48 dB and good matching across the whole band. The attenuator has a continuous controllability from DC-110GHz with an attenuation range more than 16 dB as voltage bias changed constantly varies from 0 to 1.2V. Measurements also show return loss is greater than −22dB from 10 to 110GHz. The chip size is 340×280um2 and the core area is 26×109um2.
{"title":"DC-110GHz continuous variable attenuator based on 65nm CMOS process","authors":"Jiamei Lv, J. Wen, Long Wang, Qingping Zhang, Yonghe Wang","doi":"10.1109/EDAPS.2017.8277052","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8277052","url":null,"abstract":"Continuous variable attenuator with wide bandwidth has been designed and fabricated in a 65nm CMOS process. This π-type with three shunt FETs in one side demonstrates state-of-the art performance showing a minimum insertion loss of 0.13–2.48 dB and good matching across the whole band. The attenuator has a continuous controllability from DC-110GHz with an attenuation range more than 16 dB as voltage bias changed constantly varies from 0 to 1.2V. Measurements also show return loss is greater than −22dB from 10 to 110GHz. The chip size is 340×280um2 and the core area is 26×109um2.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126125583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8277014
Karthik Rudramuni, K. Kandasamy, A. Kandwal, Qingfeng Zhang
In this paper, spoof surface plasmon polariton (SSPPs) and substrate integrated waveguide (SIW) based bandpass filter is proposed. The metal strip on the top of the substrate is composed of periodic slots which supports surface wave mode of SPP within the closed substrate integrated waveguide. The dispersion relation of the proposed structure shows that it has both low-pass feature of SSP and the high-pass feature of SIW, and hence the combination of these two features leads to a bandpass filter (BPF). The results show that the passband is from 11.5–19 GHz with relative bandwidth of 49%. Bandwidth can be controlled by properly adjusting the parameters of the design. The proposed design features a compact size and easy fabrication, due to the integration of SPP in a closed SIW.
{"title":"Compact bandpass filter based on hybrid spoof surface plasmon and substrate integrated waveguide transmission line","authors":"Karthik Rudramuni, K. Kandasamy, A. Kandwal, Qingfeng Zhang","doi":"10.1109/EDAPS.2017.8277014","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8277014","url":null,"abstract":"In this paper, spoof surface plasmon polariton (SSPPs) and substrate integrated waveguide (SIW) based bandpass filter is proposed. The metal strip on the top of the substrate is composed of periodic slots which supports surface wave mode of SPP within the closed substrate integrated waveguide. The dispersion relation of the proposed structure shows that it has both low-pass feature of SSP and the high-pass feature of SIW, and hence the combination of these two features leads to a bandpass filter (BPF). The results show that the passband is from 11.5–19 GHz with relative bandwidth of 49%. Bandwidth can be controlled by properly adjusting the parameters of the design. The proposed design features a compact size and easy fabrication, due to the integration of SPP in a closed SIW.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126633293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8277008
Jian-Chun Liu, Long Xiao, Z. Yue, Gong Zhang
The diffusion behavior of Zn in Sn-8Zn-3Bi solder joints was investigated during long-time aging at 160 °C. Intermetallic compounds (IMCs) were formed at the interface, which were identified as Ni-Zn. Thickness of the IMCs layer increased whereas the growth rate decreased with time. It was found that the growth kinetic of the IMCs was diffusion control. A diffusion model was thus proposed to describe the diffusion behavior of Zn during long-term aging, which appeared to provide a good agreement with the microstructure evolution.
{"title":"Atomic diffusion of Zn in Sn-Zn based solder joints subjected to high temperature aging","authors":"Jian-Chun Liu, Long Xiao, Z. Yue, Gong Zhang","doi":"10.1109/EDAPS.2017.8277008","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8277008","url":null,"abstract":"The diffusion behavior of Zn in Sn-8Zn-3Bi solder joints was investigated during long-time aging at 160 °C. Intermetallic compounds (IMCs) were formed at the interface, which were identified as Ni-Zn. Thickness of the IMCs layer increased whereas the growth rate decreased with time. It was found that the growth kinetic of the IMCs was diffusion control. A diffusion model was thus proposed to describe the diffusion behavior of Zn during long-term aging, which appeared to provide a good agreement with the microstructure evolution.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126834780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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