Chao-Wei Wang, Hsien-Shun Wu, Ching-Kuang C. Tzuang
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引用次数: 3
Abstract
This paper reports an on-chip synthetic transmission line (TL) with dummy fills in the standard CMOS 0.13 µm 1P8M process. The synthetic TL so-called the complementary conducting strip transmission line (CCS TL) consists of a single trace and a mesh ground plane. The dummy metals are beneath the signal trace. The measured results show the CCS TL with the dummy fills can synthesize the characteristic impedance from 35 Ω to 70 Ω without degrading the quality-factor (Q-factor). A prototype of the K-band CMOS amplifier incorporating this TL demonstrates its miniaturization, and confirms the neglected impacts on the electrical performances.