A wet process to form silicon oxide thin layer for through silicon via application

Abstract

In ultra large scale integration (ULSI) system, miniaturization of CMOS devices is becoming more and more difficult and costly, thus new fields for improving ULSI design and manufacturing are actively developed. One of the most promising ways is the three-dimensional integration of stacked chips (3D packaging). Through silicon via (TSV) technology is of significance for 3D packaging which acts as connection between chips and wafers. An insulating layer is elaborated between conductor and silicon to prevent shortcut and atom diffusion in TSV. In this paper, a wet process method to form silica layer is developed based on porous silicon (PS) and anodization. The thickness of the silica layer is well controlled by experiment factors. The morphology silicon oxide layer formed on flat silicon substrates are characterized. Comparing with traditional dry process such as thermal oxidation and chemical vapor deposition, this wet process has less requirement for equipment and can avoid some shortages of those dry processes in TSV application.