An 8.5–12.5GHz multi-PLL clock architecture with LC PLL and Ring PLL for multi-lane multi-protocol SerDes

Abstract

This paper presents a multi-PLL clock architecture used in a 4-lane multi-protocol serial link applications. The clock architecture consists of one public LC PLL and four standalone ring PLLs placed within each lane. A swtich capacitor array based LC VCO is used in the LC PLL to enlarge the frequency tuning range and decrease the VCO gain. A two stage pseudodifferential inverter based ring VCO with extra cross-coupled inverter to bring hyterisis delay for oscilating is adopted in the ring PLL. The active area occupied by the proposed LC PLL and ring PLL fabricated in SMIC 40nm CMOS technology is 0.1755mm2 and 0.049mm2. The free running VCO's phase noise at 1MHz for the LC VCO and ring VCO is −105.7dBc/Hz and −72.6dBc/Hz. The power consumption for the LC PLL and the ring PLL are 19.52mW and 16.9mW under 1.1V supply.