Low-к - package integration challenges and options for reliability qualification

A. Lucero, Guanghai Xu, D. Huitink
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引用次数: 5

Abstract

Traditional packaging materials and reliability standards are evolving as low-κ die - package integration challenges increase. The dielectric constants of low-κ die interlayer dielectric (ILD) materials are expected to continue to reduce to manage Resistance/Capacitance, RC, delay as interconnect and cell geometries are reduced. Mechanical strength is also reduced with the improvement in dielectric constant. The scaling of mechanical strength properties must be considered when designing packaging and selecting materials for packaging and assembly. Die-package integration challenges are most often observed when placing large die on flipchip packages where the differences of the coefficient of thermal expansion, CTE, between the package and die become more pronounced. In particular the underfill material and Si backend must be designed to mitigate the CTE difference by having adequate strength to carry or buffer the interfacial loads without exerting enough force to pull off the die stack films, bump interconnect or package films while at use temperatures. Properties like viscosity must also be managed for successful assembly processing. Underfill materials properties are typically coupled with the glass transition temperature, Tg, which means that the CTE and modulus properties that are required for successful assembly, use performance and reliability of the die-package system are fixed to narrow ranges. Traditional reliability standard testing and requirements do no comprehend the new reality where the Tg often falls below the traditional reliability stress test temperature. New stress test standards released by JEDEC show that lower reliability test levels with longer durations can be used to insure end user reliability in the customer use conditions. New standards have not yet been adopted by many parts of the industry, resulting in false failures and inaccurate risk assessments when the accelerated reliability test temperature ranges cause constituent materials to be artificially tested at conditions where materials properties are non-linear. Fortunately, there are many reliability characterization, analysis and reliability estimation methods that can be used to protect the end user. This paper summarizes the die-package integration challenges and trends that the industry is starting to experience along with options to select, evaluate and qualify reliable products.
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低——# x043A;-封装集成的挑战和可靠性鉴定的选择
随着低κ芯片封装集成挑战的增加,传统的封装材料和可靠性标准也在不断发展。随着互连和电池几何形状的减小,低κ芯片层间介质(ILD)材料的介电常数有望继续降低,以控制电阻/电容、RC、延迟。机械强度也随着介电常数的提高而降低。在包装设计和包装装配材料的选择中,必须考虑机械强度性能的标度问题。当在倒装芯片封装上放置大型芯片时,通常会观察到芯片封装集成方面的挑战,其中封装和芯片之间的热膨胀系数(CTE)的差异变得更加明显。特别是下填充材料和Si后端必须设计成具有足够的强度来承载或缓冲界面负载,而不会在使用温度下施加足够的力来拉掉模堆薄膜,碰撞互连或封装薄膜,从而减轻CTE差异。为了成功的装配加工,还必须管理粘度等特性。下填充材料的性能通常与玻璃化转变温度Tg耦合,这意味着成功组装所需的CTE和模量特性,使用性能和模包系统的可靠性被固定在一个狭窄的范围内。传统的可靠性标准测试和要求已不能适应新现实,即Tg往往低于传统的可靠性应力测试温度。JEDEC发布的新压力测试标准表明,可以使用较低的可靠性测试水平和较长的持续时间来确保最终用户在客户使用条件下的可靠性。新标准尚未被行业的许多部门采用,当加速可靠性测试温度范围导致成分材料在材料特性非线性的条件下进行人为测试时,导致虚假故障和不准确的风险评估。幸运的是,有许多可靠性表征、分析和可靠性估计方法可以用来保护最终用户。本文总结了模具封装集成的挑战和趋势,该行业开始经历的选择,评估和合格可靠的产品。
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