Adaptive HCI-aware power gating structure

Abstract

This paper presents the hot-carrier-injection (HCI)-induced delay degradation of the power gating structure as well as the HCI impact on critical issues in the power gating, such as leakage power, wake-up time, and wake-up rush-current. Considering this HCI impact, a novel adaptive HCI-aware power gating structure is proposed to compensate for the performance loss and the increased wake-up time of the power gating structures induced by the HCI effect. The proposed structure consists of variable width footers based on the two-pass power gating and a new HCI monitoring circuit, which is imperative for a good adaptive technique. The simulation results are compared to those of power gating without the adaptive technique and show that both the circuit-delay and wake-up time dependence of the power gating structure on the HCI stress is minimized with only 2% and 3% increase, respectively while keeping small leakage power and rush-current. The proposed technique is evaluated using ISCAS85 benchmark circuits which are designed using 45nm CMOS predictive technology model.