Toward effective utilization of timing exceptions in design optimization

Abstract

Timing exceptions in IC implementation processes, especially timing verification, help reduce pessimism that arises from unnecessary timing constraints by masking non-functional critical paths. Ideally, timing exceptions should always be helpful for quality of results (QOR) metrics such as area or number of timing violations, and for design turnaround time (TAT) metrics such as tool runtime and number of design iterations.We expect this positive impact since timing exceptions reduce the number of constraints that the design optimization must satisfy.